报告清单

[49]Characterization, Modeling and Test of SyntheticAnti-FerromagnetFlip Defect in STT-MRAMs

Lizhou Wu Post Doc. Delft University of Technology

SS /SS5 2021年08月20日 21:05~21:25

公开特邀报告

[48]Fault Modeling and Testing of Spiking Neural Network Chips

I-Wei Chiu National Taiwan University；Li James Chien Mo National Taiwan University

RS /RS1 2021年08月19日 20:40~21:00

公开口头报告

[47]A N:1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs

Danqing Li HeFei University of Technology

SS /SS1 2021年08月19日 20:40~21:00

私有口头报告

[45]Scalable Parallel Static Learning

Xiaoze Lin student Shantou University

SS /SS2 2021年08月19日 22:10~22:30

仅限参会人口头报告

[44]Learning A Wafer Feature with One Training Sample

Yueling Jenny Zeng University of California Santa Barbara

SS /SS5 2021年08月20日 22:05~22:25

仅限参会人口头报告

[43]Industrial Application of IJTAG Standards to the Test of Big-A/little-d Devices – plus Updates to the Latest State of IEEE P1687.2

Hans Martin von Staudt DIALOG SEMICONDUCTOR

SS /SS5 2021年08月20日 21:25~22:05

仅限参会人口头报告

[37]Designing Parallel TAMs for 3D-SICs Based on IEEE Std 1838’s Flexible Parallel Port Leveraging Lessons-Learned on 2D-SOCs

Erik Jan Marinissen Scientific Director imec

SS /SS3 2021年08月20日 20:40~21:00

公开口头报告

[36]Testing and Fault-Localization Solutions for Monolithic 3D ICs

Arjun Chaudhuri Duke University

SS /SS3 2021年08月20日 20:20~20:40

仅限参会人口头报告

[35]3D Test Wrapper Design and Physical Optimization

Vivek Chickermane Cadence Design Systems；Subhasish Mukherjee Cadence

SS /SS3 2021年08月20日 20:00~20:20

仅限参会人口头报告

[33]An optimized DFT technology based on machine learning

Han Yang Nanjing University of Posts and Telecommunications

SS /SS2 2021年08月19日 22:30~22:50

仅限参会人口头报告

2021 IEEE International Test Conference in Asia (ITC-Asia 2021)

[49]Characterization, Modeling and Test of SyntheticAnti-FerromagnetFlip Defect in STT-MRAMs

[48]Fault Modeling and Testing of Spiking Neural Network Chips

[47]A N:1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs

[45]Scalable Parallel Static Learning

[44]Learning A Wafer Feature with One Training Sample

[43]Industrial Application of IJTAG Standards to the Test of Big-A/little-d Devices – plus Updates to the Latest State of IEEE P1687.2

[37]Designing Parallel TAMs for 3D-SICs Based on IEEE Std 1838’s Flexible Parallel Port Leveraging Lessons-Learned on 2D-SOCs

[36]Testing and Fault-Localization Solutions for Monolithic 3D ICs

[35]3D Test Wrapper Design and Physical Optimization

[33]An optimized DFT technology based on machine learning

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