Emerging Need for Fast Thermal and Dynamic Voltage Drop Predictors for the Optimization of Scan/Functional Test Patterns
编号:9 访问权限:仅限参会人 更新:2021-08-14 15:14:24 浏览:259次 主旨报告

报告开始:2021年08月20日 10:45(Asia/Shanghai)

报告时间:45min

所在会场:[PS] Plenary Session(Openning, Keynotes 1-6) [PS2] Keynote 4/5/6

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摘要
Dr. Norman Chang, ANSYS Inc
Scan/functional testing is becoming a big challenge for large and high-power chips such as CPU/GPU/NoC and 5G chipsets. Test time optimization associated with different scan/functional test patterns is impacted by the constraints of maintaining acceptable Tj-rise and dynamic voltage drop (i.e. DvD) on-chip. Therefore, there is an emerging need for fast on-chip thermal and DvD predictors to optimize test coverage in minimum test time during pre-silicon test pattern generation. This talk will focus on the use of ML-augmented techniques for generating fast thermal and DvD data to facilitate the optimization of test pattern generation.
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报告人
Norman Chang
Chief Technologist ANSYS, Inc

Norman Chang co-founded Apache Design Solutions in February 2001 and currently serve as Ansys Fellow and Chief Technologist at Electronics and Semiconductor BU, ANSYS, Inc. Prior to Apache, he leads a group conducting PI/SI research on IA-64 chipsets at HP Labs. He is also currently leading AI/ML and security initiatives at ANSYS. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds nineteen patents and has co-authored over 50 technical papers and a popular book on “Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. He is currently in the committee for EDPS, ESDA-EDA and SI2 AI/ML SIG, and an IEEE Senior Member.

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重要日期
  • 会议日期

    08月18日

    2021

    08月20日

    2021

  • 05月10日 2021

    初稿截稿日期

  • 08月16日 2021

    提前注册日期

  • 08月19日 2021

    报告提交截止日期

  • 08月20日 2021

    注册截止日期

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