Requirements of high-speed scan and DFT implementation
编号:71 访问权限:仅限参会人 更新:2021-08-19 19:29:32 浏览:329次 口头报告

报告开始:2021年08月19日 21:05(Asia/Shanghai)

报告时间:20min

所在会场:[IS] Industrial Session [IS1] B2. The Advancement of 1149.10

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摘要
Compared chip scale increasing exponentially with Moore’s law, Scan IO bandwidth keeps stable. Using a serial high-speed interface to load-unload Scan data is a very effective solution to replace the traditional one which would make higher scan test parallelism, more reasonable Channel Compression and reduced Test System complexly.
From a semiconductor company, the presentation would introduce some industrial implementation trends or requirement to HSPHY design, Physical design, SCAN Compression and vector convert.   
The Standard’s application would be begin with Scan Data throughput to end with Test Data throughput containing Scan data, JTAG data or other data. In the end of the presentation, there is some prospective to the future of High-speed Scan technology.
关键词
High Speed SCAN;;Scan distrubution system;PCS;PHY
报告人
Fu Haitao
DFT technical expert HISILICON

Fu haitao received the B.S and M.S degree in University of Electronic Science and Technology of China, Chengdu, China, in 2007 and 2010, respectively.
In 2010, he joined Hisilicon Corporation. Now he is currently a director managing DFT technology & Solution team. His current research interests include High-speed SCAN or JTAG architecture, mixed-signal structural testing.
 

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重要日期
  • 会议日期

    08月18日

    2021

    08月20日

    2021

  • 05月10日 2021

    初稿截稿日期

  • 08月16日 2021

    提前注册日期

  • 08月19日 2021

    报告提交截止日期

  • 08月20日 2021

    注册截止日期

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Tongji University
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