A Layout Optimization Method to Reduce Commutation Inductance of Multi-Chip Power Module Based on Genetic Algorithm
编号:93 访问权限:仅限参会人 更新:2021-08-29 20:47:10 浏览:236次 口头报告

报告开始:2021年08月27日 15:45(Asia/Shanghai)

报告时间:15min

所在会场:[Room1] Oral Session 1 [S3&S4] WBG Device Applications, Package Design & Analysis

暂无文件

摘要

This paper describes an automatic optimization method for multi-chip power module (MCPM) layout based on template generation and evolutionary computation techniques. The method is developed with particular emphasis on reducing the commutation inductance and balancing the branch inductances among paralleled chips of the module. An automatic layout generation from netlist and design constraints to ready-to-fabricate prototype is carried using two-step graph-based template generation and genetic algorithm-based sizing approach. The method employs the built-in multi-port discrete circuit model for fast evaluation of layout inductance for parasitics extraction. An analytical model is also established to assist the design of embedded snubber in the post-process stage. The layout design of a 4-chip SiC module is demonstrated. Both the simulations and the experiments are conducted to illustrate the advantage of performing the automatic optimization from the initial stage of the design process.

关键词
Power Module,layout optimization,parasitic inductance,Genetic Algorithm (GA)
报告人
Yu Zhou
PhD Student Zhejiang University

稿件作者
Yu Zhou Zhejiang University
Yu Chen Zhejiang University
Hongyi Gao Zhejiang University
Chengmin Li Zhejiang University
Haoze Luo Zhejiang University
Wuhua Li Zhejiang University
Xiangning He Zhejiang University
发表评论
验证码 看不清楚,更换一张
全部评论
重要日期
  • 会议日期

    08月25日

    2021

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
联系方式
扫码在手机浏览×
H5
微信小程序码
微信小程序