Single-Pulse Avalanche Failure Characterization of Single and Paralleled SiC MOSFETs
编号:9 访问权限:公开 更新:2021-07-21 20:00:43 浏览:190次 张贴报告

报告开始:2021年08月27日 12:58(Asia/Shanghai)

报告时间:1min

所在会场:[P] Poster [P1] Poster 1

摘要
The voltage spikes generated by the turn-off of the high-speed switches can easily drive the devices into an avalanche mode and even failure. In order to study the silicon carbide (SiC) MOSFET’s avalanche limit of a single device and the influence of electrical parameters of paralleled devices, an unclamped inductance switching (UIS) test platform for single and paralleled SiC MOSFETs is set up. This paper summarizes the single-pulse avalanche limit of single MOSFET under different inductances through experiments. In addition, the characteristics of parallel connected MOSFETs under different electrical parameters are also analyzed, and the main factors that affect the avalanche failure are shown.
 
关键词
silicon carbide MOSFET,unclamped inductance switching,single-pulse avalanche
报告人
Hua Mao
Chongqing university

稿件作者
Hua Mao Chongqing university
Huaping Jiang Chongqing university
Guanqun Qiu Chongqing university
Yifu Zhang Chongqing university
Xiaohan Zhong Chongqing university
Hao Feng Chongqing university
Li Ran Chongqing university
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重要日期
  • 会议日期

    08月25日

    2021

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
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