A High Power Density Chip-on-Chip Gan-based Module with Ultra-Low Parasitic Inductance
编号:77 访问权限:仅限参会人 更新:2021-07-21 20:05:55 浏览:209次 口头报告

报告开始:2021年08月27日 16:00(Asia/Shanghai)

报告时间:15min

所在会场:[Room1] Oral Session 1 [S3&S4] WBG Device Applications, Package Design & Analysis

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摘要
A 650V/120A rated half-bridge chip-on-chip GaN module has been proposed in this paper. The chip-on-chip structure allows to distribute decoupling capacitors close to each device, which can equalize the dynamic turn-on current of parallel devices and reduce the drain-source voltage overshoot. The effect of parasitic inductance on parallel devices is analyzed and optimized. By double-sided cooling, the module shows good thermal performance.
 
关键词
GaN,modular
报告人
Yi Zhang
Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology

稿件作者
Yi Zhang Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology
Zongheng Wu Huazhong University of Science and Technology
Cai Chen Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology
Yong Kang Huazhong University of Science and Technology;School of Electrical and Electronic Engineering
Han Peng Huazhong University of Science and Technology
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重要日期
  • 会议日期

    08月25日

    2021

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
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