650V 4H-SiC VDMOS with Additional N Region_A Simulation Study
编号:2 访问权限:公开 更新:2021-08-06 15:23:45 浏览:219次 张贴报告

报告开始:2021年08月27日 13:05(Asia/Shanghai)

报告时间:1min

所在会场:[P] Poster [P1] Poster 1

摘要
Aiming at the non-uniformity of channel length caused by two-layer lithography and high resistance of channel and JFET region in 4H-SiC VDMOS, a 650V 4H-SiC VDMOS with additional N-region is investigated. Sentaurus TCAD is utilized with the 4H-SiC material parameters included in the simulations to assess the threshold voltage Vth, on-state current IDS, forward drain source blocking voltage VDSS, maximum electric field in gate oxide EOX,max, doping profile and dimension of the proposed device.The variation rules of key electrical parameters and corresponding process conditions are revealed and compared with the 650V conventional 4H-SiC VDMOS. Simulation results demonstrate that the threshold voltage Vth of 650V VDMOS with additional N-region is 0.2V higher than that of conventional VDMOS, and the specific on-state resistance RDSon,sp of 650V VDMOS with additional N-region decreased by 0.8mΩ·cm2 compared with the conventional VDMOS when the VDSS and EOX,max satisfy the design value.
 
关键词
4H-SiC;VDMOS;Additional N Region;JFET Resistance;Short channel
报告人
Xiuxiu Gao
CORESING SEMICONDUCTOR TECHNOLOGY CO . LTD

稿件作者
Xiuxiu Gao CORESING SEMICONDUCTOR TECHNOLOGY CO . LTD
发表评论
验证码 看不清楚,更换一张
全部评论
重要日期
  • 会议日期

    08月25日

    2021

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
联系方式
扫码在手机浏览×
H5
微信小程序码
微信小程序