Comparison Study of Parasitic Inductance, Capacitance and Thermal Resistance for Various SiC Packaging Structures
编号:109 访问权限:仅限参会人 更新:2021-07-21 20:06:15 浏览:222次 口头报告

报告开始:2021年08月27日 15:30(Asia/Shanghai)

报告时间:15min

所在会场:[Room1] Oral Session 1 [S3&S4] WBG Device Applications, Package Design & Analysis

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摘要
Parasitic parameters of packaging structure can affect the performance of silicon carbide (SiC) devices. Previous researches on SiC power modules lack a comprehensive comparison of different kinds of packaging structures. In this paper, six kinds of power modules are designed under the same standard, and their parasitic inductance, parasitic capacitance, and thermal resistance are extracted by finite element simulation for comparison. According to the result, the double-side-cooling structure has the smallest thermal resistance. The chip-on-chip structure shows extremely small parasitic inductance and capacitance, but this structure is complex thus the manufacturing technique and reliability should be considered. The full-shielding structure has extremely small parasitic capacitance and medial parasitic inductance, while its thermal resistance is larger than other structures. The rest three structures show mediocre performance.
关键词
SiC,packaging,thermal resistance,parasitic inductance,parasitic capacitance
报告人
Yifan Zhang
Huazhong University of Science and Technology

稿件作者
Yue Xie Huazhong University of Science and Technology
Yifan Zhang Huazhong University of Science and Technology
Cai Chen Huazhong University of Science and Technology
Yong Kang Huazhong University of Science and Technology
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重要日期
  • 会议日期

    08月25日

    2021

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
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