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A Novel Low Parasitic Inductance SiC Power Module Based on Symmetrical Planar Packaging Structure and Integrating the Laminated Busbar
编号：102 访问权限：仅限参会人 更新：2021-07-21 20:06:11 浏览：430次 口头报告

报告开始：暂无开始时间（Asia/Shanghai）

报告时间：暂无持续时间

所在会场：[暂无会议] [暂无会议段]

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摘要
This paper presents a SiC multichip power module with low parasitic inductance and symmetric layout of chips. The novelty of this module lies in the integration of a laminated busbar which can result in a significant reduction of the module parasitic inductance. Moreover, a 3D vertical structure design can reduce the commutation loop area inside the module, thereby further achieving a lower commutation loop inductance. Besides, a fan-shaped DBC layout is designed to ensure the symmetrical layout of the paralleled chips, which can realize a better current sharing performance. By the Ansys Q3D, the extracted parasitic inductance of the module is about 5.63nH, and the the imbalance degree between each parallel branch is about 5.8%. Finally, the low parasitic inductance and highly symmetry of the module are verified by the experimental tests.
关键词
Low Parasitic Inductance,current sharing,Laminated Busbar,Symmetrical design
报告人
Yuanjian Liu
HeFei University of Technology

稿件作者
Jianing Wang HeFei University of Technology；Institute of Energy,Hefei Comprehensive National Science Center
Yuanjian Liu HeFei University of Technology
Shaolin Yu HeFei University of Technology
Chen Wang HeFei University of Technology
Lijian Ding HeFei University of Technology
Nan Jiang Institute of Energy,Hefei Comprehensive National Science Center
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重要日期

  • 会议日期

    08月25日

    2021

    至

    08月27日

    2021

  • 04月21日 2021

    摘要截稿日期

  • 05月15日 2021

    摘要录用通知日期

  • 06月25日 2021

    终稿截稿日期

  • 08月24日 2021

    报告提交截止日期

  • 08月27日 2021

    注册截止日期

主办单位
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
承办单位
Huazhong University of Science and Technology
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