会议日程

(当前版本:2,更新时间:2020-03-16 17:55:56)

 

The 25th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".


Technical Program:   SIMPLE version   DETAILED version with abstract


Author Index:   HERE


Session Schedule

Tuesday, January 14, 2020

 

Room 310 Room 308 Room 307A Room 307B
1K  (Room 311)
Opening and Keynote Session I

9:00 - 10:30
1A  University Design Contest
10:45 - 12:00
1B  Machine Learning in Physical Design
10:45 - 12:00
1C  Toward Optimal Timing and PDN Design
10:45 - 12:00
1D  Side Channel Attacks and Countermeasures
10:45 - 12:00
2K  (Room 311)
Keynote Session II

12:00 - 12:40
Lunch Break
12:40 - 14:00
2A  (SS-1): Designing Reliable and Robust Circuits and Systems in the Nanometer Era
14:00 - 15:40
2B  System Architecture Innovation
14:00 - 15:40
2C  Optical Networks-on-Chips and Quantum Circuit Design
14:00 - 15:40
2D  Reliability from Design to Manufacturing
14:00 - 15:40
Coffee Break
15:40 - 16:00
3A  Reliability and Security for Deep Neural Networks
16:00 - 17:15
3B  Memory Architecture for Emerging Technologies
16:00 - 17:15
3C  Techniques for Analog Circuits and NoC
16:00 - 17:15
3D  Advanced test, verification and fault tolerance techniques
16:00 - 17:15

 



Wednesday, January 15, 2020

 

Room 310 Room 308 Room 307A Room 307B
3K  (Room 311)
Keynote Session III

9:00 - 10:00
Coffee Break
10:00 - 10:15
4A  (DF-1): Trends in EDA
10:15 - 11:30
4B  Machine-Learning and Low-Power Design
10:15 - 11:30
4C  Cryptographic Hardware Implementation and Secure Approximate Computing
10:15 - 11:30
4D  Emerging Embedded Systems Architecture
10:15 - 11:30
4K  (Room 311)
Keynote Session IV

11:30 - 12:10
Lunch Break
12:20 - 13:50
5A  Architecture and Algorithm for Deep Neural Networks
13:50 - 15:30
5B  Advanced Memory Systems
13:50 - 15:30
5C  Advances in Physical Design
13:50 - 15:30
5D  System Simulation and Exploration
13:50 - 15:30
Coffee Break
15:30 - 15:45
6A  (SS-2): Computation-in-Memory based on emerging non-volatile memories: Technology, design, and test and reliability
15:45 - 17:00
6B  (SS-3): Emerging Memory Enabled Computing in The Post-Moore’s Era
15:45 - 17:25
6C  (SS-4): AI Enhanced Simulation and Optimization in Back-End EDA Flow
15:45 - 17:00
6D  (DF-2): Emerging Design
15:45 - 17:00
5K  (Room 311)
Keynote Session V

17:30 - 18:10
Banquet (Room 311)
18:30 - 20:00

 



Thursday, January 16, 2020

 

Room 310 Room 308 Room 307A Room 307B
6K  (Room 311)
Keynote Session VI

9:00 - 10:00
Coffee Break
10:00 - 10:15
7A  Neuromorphic Computing
10:15 - 11:30
7B  Machine Learning for Embedded Systems
10:15 - 11:30
7C  Malicious Activities Generation and Detection
10:15 - 11:30
7D  Embedded Software for Energy Optimization and Non-Volatile Memory
10:15 - 11:30
Lunch Break
11:30 - 13:50
8A  Search and Optimization for Deep Neural Networks
13:50 - 15:30
8B  FPGAs for Big Data Systems, Nonvolatile Computing, and Microfluidics
13:50 - 15:30
8C  Advances in Logic/High-Level Synthesis
13:50 - 15:30
8D  Scalable and Reconfigurable Approximate Arithmetic Units
13:50 - 15:30
Coffee Break
15:30 - 15:45
9A  (SS-5): Resilience in Integrated Systems
15:45 - 17:00
9B  (SS-6): Emerging Technologies across the Abstraction Layers
15:45 - 17:00
9C  (SS-7): CMOS Annealing Hardware: Pursuing Efficiency for Solving Combinatorial Optimization Problems
15:45 - 17:00
9D  (DF-3): AI Accelerators
15:45 - 17:00

 



DF: Designers' Forum, SS: Special Session


 

List of papers

Remark: The presenter of each paper is marked with "*".


 

Tuesday, January 14, 2020

 


Session 1K  Opening and Keynote Session I
Time: 9:00 - 10:30 Tuesday, January 14, 2020
Location: Room 311

 

1K-1 (Time: 9:30 - 10:30)

Title (Keynote Address) Skin Electronics for Continuous Health Monitoring
Author Takao Someya (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

 



Session 1A  University Design Contest
Time: 10:45 - 12:00 Tuesday, January 14, 2020
Location: Room 310
Chair: Dajiang Liu (Chongqing Univ.)

 

1A-1 (Time: 10:45 - 10:48)

Title Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications
Author *Lin Cheng (Univ. of Science and Tech. of China, China), Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., China), Ming Liu (Institute of Microelectronics, Chinese Academy of Sciences,, China)
Page pp. 1 - 2
Detailed information (abstract, keywords, etc)

 

1A-2 (Time: 10:48 - 10:51)

Title A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 um CMOS
Author Sujin Park (KAIST, Republic of Korea), Geon-Hwi Lee (KAIST/SK Hynix, Republic of Korea), *Seungmin Oh, SeongHwan Cho (KAIST, Republic of Korea)
Page pp. 3 - 4
Detailed information (abstract, keywords, etc)

 

1A-3 (Time: 10:51 - 10:54)

Title A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR
Author *Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Page pp. 5 - 6
Detailed information (abstract, keywords, etc)

 

1A-4 (Time: 10:54 - 10:57)

Title A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System
Author *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Page pp. 7 - 8
Detailed information (abstract, keywords, etc)

 

1A-5 (Time: 10:57 - 11:00)

Title An Inductively Coupled Wireless Bus for Chiplet-Based Systems
Author *Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai (Univ. of Tokyo, Japan)
Page pp. 9 - 10
Detailed information (abstract, keywords, etc)

 

1A-6 (Time: 11:00 - 11:03)

Title FPGA-based Heterogeneous Solver for Three-Dimensional Routing
Author Kento Hasegawa, *Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa (Waseda Univ., Japan)
Page pp. 11 - 12
Detailed information (abstract, keywords, etc)

 



Session 1B  Machine Learning in Physical Design
Time: 10:45 - 12:00 Tuesday, January 14, 2020
Location: Room 308
Chair: Iris Hui-Ru Jiang (National Taiwan Univ.)

 

1B-1 (Time: 10:45 - 11:10)

Title PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Author *Zhiyao Xie (Duke Univ., USA), Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh (Nvidia, USA), Jiang Hu (TAMU, USA), Yiran Chen (Duke Univ., USA)
Page pp. 13 - 18
Detailed information (abstract, keywords, etc)

 

1B-2 (Time: 11:10 - 11:35)

Title FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Author *Zhiyao Xie (Duke Univ., USA), Guan-Qi Fang, Yu-Hung Huang (National Taiwan Univ. of Science and Tech., Taiwan), Haoxing Ren, Yanqing Zhang, Brucek Khailany (Nvidia, USA), Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Jiang Hu (TAMU, USA), Yiran Chen (Duke Univ., USA), Erick Carvajal Barboza (TAMU, USA)
Page pp. 19 - 25
Detailed information (abstract, keywords, etc)

 

1B-3 (Time: 11:35 - 12:00)

Title High-Definition Routing Congestion Prediction for Large-Scale FPGAs
Author Mohamed Baker Alawieh, Wuxi Li, *Yibo Lin (Univ. of Texas, Austin, USA), Love Singhal, Mahesh A. Iyer (Intel, USA), David Z. Pan (Univ. of Texas, Austin, USA)
Page pp. 26 - 31
Detailed information (abstract, keywords, etc)

 



Session 1C  Toward Optimal Timing and PDN Design
Time: 10:45 - 12:00 Tuesday, January 14, 2020
Location: Room 307A
Chairs: Yu-Guang Chen (National Central Univ., Taiwan), Jianglei Yang (Beihang Univ.)

 

1C-1 (Time: 10:45 - 11:10)

Title Integrated Airgap Insertion and Layer Reassignment for Circuit Timing Optimization
Author *Younggwang Jung, Daijoon Hyun, Youngsoo Shin (KAIST, Republic of Korea)
Page pp. 32 - 37
Detailed information (abstract, keywords, etc)

 

1C-2 (Time: 11:10 - 11:35)

Title An Adaptive Electromigration Assessment Algorithm for Full-chip Power/Ground Networks
Author *Shaobin Ma, Xiaoyi Wang (Beijing Univ. of Tech., China), Sheldon X.-D. Tan, Liang Chen (Univ. of California, Riverside, USA), Jian He (Beijing Univ. of Tech., China)
Page pp. 38 - 43
Detailed information (abstract, keywords, etc)

 

1C-3 (Time: 11:35 - 12:00)

Title Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques
Author *Vidya A. Chhabria (Univ. of Minnesota, USA), Andrew B. Kahng, Minsoo Kim, Uday Mallappa (Univ. of California, San Diego, USA), Sachin S. Sapatnekar (Univ. of Minnesota, USA), Bangqi Xu (Univ. of California, San Diego, USA)
Page pp. 44 - 49
Detailed information (abstract, keywords, etc)

 



Session 1D  Side Channel Attacks and Countermeasures
Time: 10:45 - 12:00 Tuesday, January 14, 2020
Location: Room 307B
Chairs: Hiromitsu Awano (Osaka Univ., Japan), Song Bian (Kyoto Univ., Japan)

 

1D-1 (Time: 10:45 - 11:10)

Title Analyzing The Security of The Cache Side Channel Defences With Attack Graphs
Author *Limin Wang, Ziyuan Zhu, Zhanpeng Wang, Dan Meng (Chinese Academy of Sciences, China)
Page pp. 50 - 55
Detailed information (abstract, keywords, etc)

 

1D-2 (Time: 11:10 - 11:35)

Title iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU
Author *Wenjian He, Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Sharad Sinha (Indian Inst. of Tech. Goa, India), Sanjeev Das (Univ. of North Carolina, Chapel Hill, USA)
Page pp. 56 - 61
Detailed information (abstract, keywords, etc)

 

1D-3 (Time: 11:35 - 12:00)

Title Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations
Author *Jiaji He (Tsinghua Univ., China), Haocheng Ma (Tianjin Univ., China), Xiaolong Guo (Kansas State Univ., USA), Yiqiang Zhao (Tianjin Univ., China), Yier Jin (Univ. of Florida, USA)
Page pp. 62 - 67
Detailed information (abstract, keywords, etc)

 



Session 2K  Keynote Session II
Time: 12:00 - 12:40 Tuesday, January 14, 2020
Location: Room 311

 

2K-1 (Time: 12:00 - 12:40)

Title (Keynote Address) Edge-to-Cloud Innovations for Inclusive AI
Author Xiaoning Qi (Alibaba)
Detailed information (abstract, keywords, etc)

 



Session 2A  (SS-1): Designing Reliable and Robust Circuits and Systems in the Nanometer Era
Time: 14:00 - 15:40 Tuesday, January 14, 2020
Location: Room 310
Chair: Sheldon Tan (Univ. of California Riverside, USA)

 

2A-1 (Time: 14:00 - 14:25)

Title (Invited Paper) Impact of Self-Heating On Performance, Power and Reliability in FinFET Technology
Author Victor M. van Santen, Paul R. Genssler, Om Prakash, Simon Thomann, Jörg Henkel, *Hussam Amrouch (Karlsruhe Inst. of Tech., Germany)
Page pp. 68 - 73
Detailed information (abstract, keywords, etc)

 

2A-2 (Time: 14:25 - 14:50)

Title (Invited Paper) Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment Wires
Author Han Zhou, Shuyuan Yu, Zeyu Sun, *Sheldon X.-D. Tan (Univ. of California, Riverside, USA)
Page pp. 74 - 79
Detailed information (abstract, keywords, etc)

 

2A-3 (Time: 14:50 - 15:15)

Title (Invited Paper) Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation
Author Uzair Sharif, Daniel Müller-Gritschneder, *Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page pp. 80 - 84
Detailed information (abstract, keywords, etc)

 



Session 2B  System Architecture Innovation
Time: 14:00 - 15:40 Tuesday, January 14, 2020
Location: Room 308
Chair: Eric Liang (Peking Universtiy)

 

2B-1 (Time: 14:00 - 14:25)

Title Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence
Author *Lei Yang (Univ. of Pittsburgh, USA), Weiwen Jiang (Univ. of Notre Dame, USA), Weichen Liu (Nanyang Technological Univ., Singapore), Edwin H. M. Sha (East China Normal Univ., China), Yiyu Shi (Univ. of Notre Dame, USA), Jingtong Hu (Univ. of Pittsburgh, USA)
Page pp. 85 - 90
Detailed information (abstract, keywords, etc)

 

2B-2 (Time: 14:25 - 14:50)

Title Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition
Author Dae Hee Kim, Rakesh Nagi, *Deming Chen (Univ. of Illinois, Urbana-Champaign, USA)
Page pp. 91 - 96
Detailed information (abstract, keywords, etc)

 

2B-3 (Time: 14:50 - 15:15)

Title Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs
Author *Sidhartha Sankar Rout, Badri M, Sujay Deb (Indraprastha Institute of Information Technology, Delhi, India)
Page pp. 97 - 102
Detailed information (abstract, keywords, etc)

 

2B-4 (Time: 15:15 - 15:40)

Title Formal Semantics of Predictable Pipelines: a Comparative Study
Author Mathieu Jan, *Mihail Asavoae (CEA LIST, France), Martin Schoeberl (Tech. Univ. of Denmark, Denmark), Edward A. Lee (Univ. of California, Berkeley, USA)
Page pp. 103 - 108
Detailed information (abstract, keywords, etc)

 



Session 2C  Optical Networks-on-Chips and Quantum Circuit Design
Time: 14:00 - 15:40 Tuesday, January 14, 2020
Location: Room 307A
Chairs: Rudy Raymond H.P. (IBM Research, Japan), Shigeru Yamashita (Ritsumeikan Univ.)

 

2C-1 (Time: 14:00 - 14:25)

Title Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-on-Chips
Author *Mengchu Li, Tsun-Ming Tseng (Tech. Univ. of Munich, Germany), Mahdi Tala (Univ. of Ferrara, Italy), Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page pp. 109 - 114
Detailed information (abstract, keywords, etc)

 

2C-2 (Time: 14:25 - 14:50)

Title Concurrency in DD-based Quantum Circuit Simulation
Author *Stefan Hillmich, Alwin Zulehner, Robert Wille (Johannes Kepler Univ. Linz Institute for Integrated Circuits, Austria)
Page pp. 115 - 120
Detailed information (abstract, keywords, etc)

 

2C-3 (Time: 14:50 - 15:15)

Title Approximation of Quantum States Using Decision Diagrams
Author Alwin Zulehner, Stefan Hillmich (Johannes Kepler Univ. Linz Institute for Integrated Circuits, Austria), Igor L. Markov (Univ. of Michigan, USA), *Robert Wille (Johannes Kepler Univ. Linz Institute for Integrated Circuits, Austria)
Page pp. 121 - 126
Detailed information (abstract, keywords, etc)

 

2C-4 (Time: 15:15 - 15:40)

Title Improved DD-based Equivalence Checking of Quantum Circuits
Author *Lukas Burgholzer, Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page pp. 127 - 132
Detailed information (abstract, keywords, etc)

 



Session 2D  Reliability from Design to Manufacturing
Time: 14:00 - 15:40 Tuesday, January 14, 2020
Location: Room 307B
Chair: Changhao Yan (Fudan Univ., China)

 

2D-1 (Time: 14:00 - 14:25)

Title Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
Author *Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang (National Taiwan Univ., Taiwan)
Page pp. 133 - 138
Detailed information (abstract, keywords, etc)

 

2D-2 (Time: 14:25 - 14:50)

Title Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes
Author *Jeongwoo Heo (Seoul National Univ., Republic of Korea), Kwangok Jeong (Samsung Electronics, Republic of Korea), Taewhan Kim, Kyumyung Choi (Seoul National Univ., Republic of Korea)
Page pp. 139 - 144
Detailed information (abstract, keywords, etc)

 

2D-3 (Time: 14:50 - 15:15)

Title Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation
Author Chaofei Yang, Hai Li, *Yiran Chen (Duke Univ., USA), Jiang Hu (Texas A&M Univ., USA)
Page pp. 145 - 150
Detailed information (abstract, keywords, etc)

 

2D-4 (Time: 15:15 - 15:40)

Title Exploring Graphical Models with Bayesian Learning and MCMC for Failure Diagnosis
Author *Hongfei Wang, Wenjie Cai, Jianwen Li, Kun He (Huazhong Univ. of Science and Tech., China)
Page pp. 151 - 156
Detailed information (abstract, keywords, etc)

 



Session 3A  Reliability and Security for Deep Neural Networks
Time: 16:00 - 17:15 Tuesday, January 14, 2020
Location: Room 310
Chair: Andrew Putnam (Microsoft, USA)

 

3A-1 (Time: 16:00 - 16:25)

Title Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation
Author *Pengfei Qiu (Tsinghua Univ., China), Qian Wang (Univ. of Maryland, College Park, USA), Dongsheng Wang, Yongqiang Lyu (Tsinghua Univ., China), Zhaojun Lu, Gang Qu (Univ. of Maryland, College Park, USA)
Page pp. 157 - 162
Detailed information (abstract, keywords, etc)

 

3A-2 (Time: 16:25 - 16:50)

Title When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
Author Zheyu Yan (Zhejiang Univ., China), Yiyu Shi (Univ. of Notre Dame, USA), Wang Liao, Masanori Hashimoto (Osaka Univ., Japan), Xichuan Zhou (Chongqing Univ., China), *Cheng Zhuo (Zhejiang Univ., China)
Page pp. 163 - 168
Detailed information (abstract, keywords, etc)

 

3A-3 (Time: 16:50 - 17:15)

Title Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions
Author Elbruz Ozen, *Alex Orailoglu (Univ. of California, San Diego, USA)
Page pp. 169 - 174
Detailed information (abstract, keywords, etc)

 



Session 3B  Memory Architecture for Emerging Technologies
Time: 16:00 - 17:15 Tuesday, January 14, 2020
Location: Room 308
Chairs: Dongsuk Jeon (Seoul National Univ.), Xianzhang Chen (Chongqing Univ.)

 

3B-1 (Time: 16:00 - 16:25)

Title PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM
Author *Fan Chen, Linghao Song, Hai "Helen" Li, Yiran Chen (Duke Univ., USA)
Page pp. 175 - 180
Detailed information (abstract, keywords, etc)

 

3B-2 (Time: 16:25 - 16:50)

Title RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures
Author *Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza (Swiss Federal Inst. of Tech. (EPFL), Switzerland)
Page pp. 181 - 186
Detailed information (abstract, keywords, etc)

 

3B-3 (Time: 16:50 - 17:15)

Title Defects Mitigation in Resistive Crossbars for Analog Vector/Matrix Multiplication
Author *Fan Zhang, Miao Hu (Binghamton Univ., USA)
Page pp. 187 - 192
Detailed information (abstract, keywords, etc)

 



Session 3C  Techniques for Analog Circuits and NoC
Time: 16:00 - 17:15 Tuesday, January 14, 2020
Location: Room 307A
Chairs: Markus Olbrich (Leibniz Univ. Hannover, Germany), Fan Yang (Fudan Univ., China)

 

3C-1 (Time: 16:00 - 16:25)

Title S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity
Author Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, *Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan (Univ. of Texas, Austin, USA)
Page pp. 193 - 198
Detailed information (abstract, keywords, etc)

 

3C-2 (Time: 16:25 - 16:50)

Title Establishing Reachset Conformance for the Formal Analysis of Analog Circuits
Author *Niklas Kochdumper (Tech. Univ. of Munich, Germany), Ahmad Tarraf (Goethe Univ. Frankfurt, Germany), Malgorzata Rechmal, Markus Olbrich (Leibniz Univ. Hannover, Germany), Lars Hedrich (Goethe Univ. Frankfurt, Germany), Matthias Althoff (Tech. Univ. of Munich, Germany)
Page pp. 199 - 204
Detailed information (abstract, keywords, etc)

 

3C-3 (Time: 16:50 - 17:15)

Title Contention Minimized Bypassing in SMART NoC
Author *Peng Chen (Nanyang Technological Univ./Chongqing Univ., Singapore), Weichen Liu (Nanyang Technological Univ., Singapore), Mengquan Li (Nanyang Technological Univ./Chongqing Univ., Singapore), Lei Yang (Univ. of Pittsburgh, USA), Nan Guan (Hong Kong Polytechnic Univ., Hong Kong)
Page pp. 205 - 210
Detailed information (abstract, keywords, etc)

 



Session 3D  Advanced test, verification and fault tolerance techniques
Time: 16:00 - 17:15 Tuesday, January 14, 2020
Location: Room 307B
Chairs: Ying Zhang (Tongji Univ., China), Michihiro Shintani (NAIST, Japan)

 

3D-1 (Time: 16:00 - 16:25)

Title FTT-NAS: Discovering Fault-Tolerant Neural Architecture
Author *Wenshuo Li, Xuefei Ning, Guangjun Ge (Tsinghua Univ., China), Xiaoming Chen (State Key Laboratory of Computer Architecture, Institute of Computing Technology, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page pp. 211 - 216
Detailed information (abstract, keywords, etc)

 

3D-2 (Time: 16:25 - 16:50)

Title The Notion of Cross Coverage in AMS Design Verification
Author Sayandeep Sanyal, Aritra Hazra, *Pallab Dasgupta (Indian Inst. of Tech. Kharagpur, India), Scott Morrison (Texas Instruments, USA), Sudhakar Surendran, Lakshmanan Balasubramanian (Texas Instruments (India) Pvt., India)
Page pp. 217 - 222
Detailed information (abstract, keywords, etc)

 

3D-3 (Time: 16:50 - 17:15)

Title Automated Test Generation for Activation of Assertions in RTL Models
Author *Yangdi Lyu, Prabhat Mishra (Univ. of Florida, USA)
Page pp. 223 - 228
Detailed information (abstract, keywords, etc)

 


 

Wednesday, January 15, 2020

 


Session 3K  Keynote Session III
Time: 9:00 - 10:00 Wednesday, January 15, 2020
Location: Room 311

 

3K-1 (Time: 9:00 - 10:00)

Title (Keynote Address) Design Automation for Customizable Computing
Author Jason Cong (Univ. of California, Los Angles, USA)
Detailed information (abstract, keywords, etc)

 



Session 4A  (DF-1): Trends in EDA
Time: 10:15 - 11:30 Wednesday, January 15, 2020
Location: Room 310
Chair: Bei Yu (Chinese Univ. of Hong Kong)

 

4A-1 (Time: 10:15 - 10:40)

Title (Designers' Forum) The Golden Age of EDA — Clock Design, Machine Learning and A-I Collaboration
Author Zhuo Li (Cadence design systems, USA)
Detailed information (abstract, keywords, etc)

 

4A-2 (Time: 10:40 - 11:05)

Title (Designers' Forum) New Trend on High-Level Synthesis and Customized Compiler for Edge Intelligence
Author Deming Chen (UIUC, USA)
Detailed information (abstract, keywords, etc)

 

4A-3 (Time: 11:05 - 11:30)

Title (Designers' Forum) Data-driven Instant Model Synthesis Enhanced by Learning Algorithms For DTCO Enablement In the FinFET Era
Author Yanfeng Li (Platform Design Automation, China)
Detailed information (abstract, keywords, etc)

 



Session 4B  Machine-Learning and Low-Power Design
Time: 10:15 - 11:30 Wednesday, January 15, 2020
Location: Room 308
Chairs: Cheng Zhuo (Zhejiang Univ., China), Hai Wang (UESTC, China)

 

4B-1 (Time: 10:15 - 10:40)

Title Machine Learning Based Online Full-Chip Heatmap Estimation
Author Sheriff Sadiqbatcha, Yue Zhao, Jinwei Zhang (Univ. of California, Riverside, USA), Hussam Amrouch, Joerg Henkel (Karlsruhe Inst. of Tech., Germany), *Sheldon X.-D. Tan (Univ. of California, Riverside, USA)
Page pp. 229 - 234
Detailed information (abstract, keywords, etc)

 

4B-2 (Time: 10:40 - 11:05)

Title A Reconfigurable Approximate Multiplier for Quantized CNN Applications
Author *Chuliang Guo, Li Zhang, Xian Zhou (Zhejiang Univ., China), Weikang Qian (Shanghai Jiao Tong Univ., China), Cheng Zhuo (Zhejiang Univ., China)
Page pp. 235 - 240
Detailed information (abstract, keywords, etc)

 

4B-3 (Time: 11:05 - 11:30)

Title EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit
Author *Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang (Utah State Univ., USA)
Page pp. 241 - 246
Detailed information (abstract, keywords, etc)

 



Session 4C  Cryptographic Hardware Implementation and Secure Approximate Computing
Time: 10:15 - 11:30 Wednesday, January 15, 2020
Location: Room 307A
Chair: Weiqiang Liu (Nanjing Univ. of Aeronautics and Astronautics, China)

 

4C-1 (Time: 10:15 - 10:40)

Title Towards Efficient Kyber on FPGAs: A Processor for Vector of Polynomials
Author *Zhaohui Chen (Univ. of Chinese Academy of Sciences, China), Yuan Ma, Tianyu Chen, Jingqiang Lin (Chinese Academy of Sciences, China), Jiwu Jing (Univ. of Chinese Academy of Sciences, China)
Page pp. 247 - 252
Detailed information (abstract, keywords, etc)

 

4C-2 (Time: 10:40 - 11:05)

Title Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation
Author Chiou-Yng Lee (Lunghwa Univ. of Science and Tech., Taiwan), *Jiafeng Xie (Villanova Univ., USA)
Page pp. 253 - 258
Detailed information (abstract, keywords, etc)

 

4C-3 (Time: 11:05 - 11:30)

Title Security Threats and Countermeasures for Approximate Arithmetic Computing
Author *Pruthvy Yellu, Mezanur Rahman Monjur, Timothy Kammerer, Dongpeng Xu, Qiaoyan Yu (Univ. of New Hampshire, USA)
Page pp. 259 - 264
Detailed information (abstract, keywords, etc)

 



Session 4D  Emerging Embedded Systems Architecture
Time: 10:15 - 11:30 Wednesday, January 15, 2020
Location: Room 307B

 

4D-1 (Time: 10:15 - 10:40)

Title Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing
Author Hemanta Kumar Mondal (National Inst. of Tech. Durgapur, India), *Navonil Chatterjee, Rodrigo Cataldo, Jean-Philippe Diguet (Univ. de Bretagne Sud, France)
Page pp. 265 - 270
Detailed information (abstract, keywords, etc)

 

4D-2 (Time: 10:40 - 11:05)

Title A Generic FPGA Accelerator for Minimum Storage Regenerating Codes
Author Mian Qin (Texas A&M Univ., USA), Joo Hwan Lee, Rekha Pitchumani, Yang Seok Ki (Samsung Semiconductor, USA), Narasimha Reddy, *Paul V. Gratz (Texas A&M Univ., USA)
Page pp. 271 - 276
Detailed information (abstract, keywords, etc)

 

4D-3 (Time: 11:05 - 11:30)

Title Parallel-Log-Single-Compaction-Tree: Flash-Friendly Two-Level Key-Value Management in KVSSDs
Author *Yen-Ting Chen (National Tsing Hua Univ., Taiwan), Ming-Chang Yang (Chinese Univ. of Hong Kong, Hong Kong), Yuan-Hao Chang (Academia Sinica, Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan)
Page pp. 277 - 282
Detailed information (abstract, keywords, etc)

 



Session 4K  Keynote Session IV
Time: 11:30 - 12:10 Wednesday, January 15, 2020
Location: Room 311

 

4K-1 (Time: 11:30 - 12:10)

Title (Keynote Address) Huge Development of RISC-V Arising from IOT Spurt
Author Yingwu Zhang (GigaDevice, China)
Detailed information (abstract, keywords, etc)

 



Session 5A  Architecture and Algorithm for Deep Neural Networks
Time: 13:50 - 15:30 Wednesday, January 15, 2020
Location: Room 310
Chair: Deming Chen (UIUC)

 

5A-1 (Time: 13:50 - 14:15)

Title Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAs
Author Jung-Woo Chang, *Saehyun Ahn, Keon-Woo Kang, Suk-Ju Kang (Sogang Univ., Republic of Korea)
Page pp. 283 - 288
Detailed information (abstract, keywords, etc)

 

5A-2 (Time: 14:15 - 14:40)

Title Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator
Author *Baoting Li, Longjun Liu, Yanming Jin, Peng Gao, Hongbin Sun, Nanning Zheng (Xi'an Jiaotong Univ., China)
Page pp. 289 - 294
Detailed information (abstract, keywords, etc)

 

5A-3 (Time: 14:40 - 15:05)

Title CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures
Author Maedeh Hemmat, *Tejas Shah, Yuhua Chen, Joshua San Miguel (Univ. of Wisconsin Madison, USA)
Page pp. 295 - 300
Detailed information (abstract, keywords, etc)

 

5A-4 (Time: 15:05 - 15:30)

Title Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN Implementation
Author Xiaolong Ma, Geng Yuan, *Sheng Lin (Northeastern Univ., USA), Caiwen Ding (Univ. of Connecticut, USA), Fuxun Yu (George Mason Univ., USA), Tao Liu (Florida International Univ., USA), Wujie Wen (Lehigh Univ., USA), Xiang Chen (George Mason Univ., USA), Yanzhi Wang (Northeastern Univ., USA)
Page pp. 301 - 306
Detailed information (abstract, keywords, etc)

 



Session 5B  Advanced Memory Systems
Time: 13:50 - 15:30 Wednesday, January 15, 2020
Location: Room 308
Chairs: Ing-Chao Lin (National Cheng Kung Univ.), Guangyu Sun (Peking Univ.)

 

5B-1 (Time: 13:50 - 14:15)

Title Towards Read-Intensive Key-Value Stores with Tidal Structure Based on LSM-Tree
Author *Yi Wang, Shangyu Wu, Rui Mao (Shenzhen Univ., China)
Page pp. 307 - 312
Detailed information (abstract, keywords, etc)

 

5B-2 (Time: 14:15 - 14:40)

Title A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks
Author Li Yang (Arizona State Univ., USA), Shaahin Angizi (Univ. of Central Florida, USA), *Deliang Fan (Arizona State Univ., USA)
Page pp. 313 - 318
Detailed information (abstract, keywords, etc)

 

5B-3 (Time: 14:40 - 15:05)

Title Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance
Author *Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi (Chuo Univ., Japan)
Page pp. 319 - 324
Detailed information (abstract, keywords, etc)

 

5B-4 (Time: 15:05 - 15:30)

Title An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators
Author *Hanbo Sun, Zhenhua Zhu, Yi Cai (Tsinghua Univ., China), Xiaoming Chen (Chinese Academy of Sciences, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page pp. 325 - 330
Detailed information (abstract, keywords, etc)

 



Session 5C  Advances in Physical Design
Time: 13:50 - 15:30 Wednesday, January 15, 2020
Location: Room 307A
Chairs: Jiang Hu (TAMU), Jianli Chen (Fuzhou Univ.)

 

5C-1 (Time: 13:50 - 14:15)

Title Unified Redistribution Layer Routing for 2.5D IC Packages
Author Chun-Han Chiang, *Fu-Yu Chuang, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page pp. 331 - 337
Detailed information (abstract, keywords, etc)

 

5C-2 (Time: 14:15 - 14:40)

Title AIR: A Fast but Lazy Timing-Driven FPGA Router
Author *Kevin E. Murray, Shen Zhong, Vaughn Betz (Univ. of Toronto, Canada)
Page pp. 338 - 344
Detailed information (abstract, keywords, etc)

 

5C-3 (Time: 14:40 - 15:05)

Title SP&R: Simultaneous Placement and Routing Framework for Standard Cell Synthesis in Sub-7nm
Author Dongwon Park, *Daeyeal Lee (Univ. of California, San Diego, USA), Ilgweon Kang (Cadence, USA), Sicun Gao, Bill Lin, Chung-Kuan Cheng (Univ. of California, San Diego, USA)
Page pp. 345 - 350
Detailed information (abstract, keywords, etc)

 

5C-4 (Time: 15:05 - 15:30)

Title Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools
Author MD Arafat Kabir, *Yarui Peng (Univ. of Arkansas, USA)
Page pp. 351 - 356
Detailed information (abstract, keywords, etc)

 



Session 5D  System Simulation and Exploration
Time: 13:50 - 15:30 Wednesday, January 15, 2020
Location: Room 307B
Chairs: Weichen Liu (Nanyang Technological Univ., Singapore), Eric Liang (Peking Univ., China)

 

5D-1 (Time: 13:50 - 14:15)

Title Event Delivery using Prediction for Faster Parallel SystemC Simulation
Author *Zhongqi Cheng, Emad Arasteh, Rainer Dömer (Univ. of California, Irvine, USA)
Page pp. 357 - 362
Detailed information (abstract, keywords, etc)

 

5D-2 (Time: 14:15 - 14:40)

Title Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models
Author *Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux (CEA, LIST, Computing and Design Environment Laboratory, France), Matthieu Moy (Univ Lyon, EnsL, UCBL, CNRS, Inria, LIP, France)
Page pp. 363 - 368
Detailed information (abstract, keywords, etc)

 

5D-3 (Time: 14:40 - 15:05)

Title JIT-Based Context-Sensitive Timing Simulation for Efficient Platform Exploration
Author *Alessandro Cornaglia, Md Shakib Hasan, Alexander Viehl (FZI Research Center for Information Technology, Germany), Oliver Bringmann, Wolfgang Rosenstiel (Univ. of Tübingen, Germany)
Page pp. 369 - 374
Detailed information (abstract, keywords, etc)

 

5D-4 (Time: 15:05 - 15:30)

Title Towards Automatic Hardware Synthesis from Formal Specification to Implementation
Author *Fritjof Bornebusch, Christoph Lüth (German Research Center for Artificial Intelligence (DFKI), Germany), Robert Wille (Johannes Kepler Univ. Linz, Austria), Rolf Drechsler (Univ. of Bremen, Germany)
Page pp. 375 - 380
Detailed information (abstract, keywords, etc)

 



Session 6A  (SS-2): Computation-in-Memory based on emerging non-volatile memories: Technology, design, and test and reliability
Time: 15:45 - 17:00 Wednesday, January 15, 2020
Location: Room 310
Chair: Mehdi Tahoori (Faculty of Informatik, Karlsruhe Inst. of Tech. (KIT), Germany)

 

6A-1 (Time: 15:45 - 16:10)

Title (Invited Paper) Emerging Non-Volatile Memories for Computation-in-Memory
Author *Bin Gao (Tsinghua Univ., China)
Page pp. 381 - 384
Detailed information (abstract, keywords, etc)

 

6A-2 (Time: 16:10 - 16:35)

Title (Invited Paper) The Power of Computation-in-Memory Based on Memristive Devices
Author *Jintao Yu, Muath Abu Lebdeh, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui (Delft Univ. of Tech., Netherlands)
Page pp. 385 - 392
Detailed information (abstract, keywords, etc)

 

6A-3 (Time: 16:35 - 17:00)

Title (Invited Paper) Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories
Author Christopher Münch (Karlsruhe Inst. of Tech., Germany), Rajendra Bishnoi (Delft Univ. of Tech., Netherlands), *Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Page pp. 393 - 400
Detailed information (abstract, keywords, etc)

 



Session 6B  (SS-3): Emerging Memory Enabled Computing in The Post-Moore’s Era
Time: 15:45 - 17:25 Wednesday, January 15, 2020
Location: Room 308
Chair: Xueqing Li (Tsinghua Univ., China)

 

6B-1 (Time: 15:45 - 16:10)

Title (Invited Paper) Ferroelectrics: From Memory to Computing
Author *Kai Ni (Rochester Inst. of Tech., USA), Sourav Dutta, Suman Datta (Univ. of Notre Dame, USA)
Page pp. 401 - 406
Detailed information (abstract, keywords, etc)

 

6B-2 (Time: 16:10 - 16:35)

Title (Invited Paper) Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory
Author Juejian Wu, Yixin Xu, Bowen Xue, Yu Wang, Yongpan Liu, Huazhong Yang, *Xueqing Li (Tsinghua Univ., China)
Page pp. 407 - 413
Detailed information (abstract, keywords, etc)

 

6B-3 (Time: 16:35 - 17:00)

Title (Invited Paper) Emerging Memories as Enablers for In-Memory Layout Transformation Acceleration and Virtualization
Author Minli Liao, *John (Jack) Sampson (Pennsylvania State Univ., USA)
Page pp. 414 - 421
Detailed information (abstract, keywords, etc)

 

6B-4 (Time: 17:00 - 17:25)

Title (Invited Paper) Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training
Author Yandong Luo, *Shimeng Yu (Georgia Tech, USA)
Page pp. 422 - 427
Detailed information (abstract, keywords, etc)

 



Session 6C  (SS-4): AI Enhanced Simulation and Optimization in Back-End EDA Flow
Time: 15:45 - 17:00 Wednesday, January 15, 2020
Location: Room 307A
Chair: Wenjian Yu (Tsinghua Univ., China)

 

6C-1 (Time: 15:45 - 16:10)

Title (Invited Paper) Capacitance Extraction and Power Grid Analysis Using Statistical and AI Methods
Author *Wenjian Yu, Ming Yang, Yao Feng, Ganqu Cui (Tsinghua Univ., China), Ben Gu (Cadence, USA)
Page pp. 428 - 433
Detailed information (abstract, keywords, etc)

 

6C-2 (Time: 16:10 - 16:35)

Title (Invited Paper) VLSI Mask Optimization: From Shallow To Deep Learning
Author *Haoyu Yang (Chinese Univ. of Hong Kong, Hong Kong), Wei Zhong (Dalian Univ. of Tech., China), Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page pp. 434 - 439
Detailed information (abstract, keywords, etc)

 

6C-3 (Time: 16:35 - 17:00)

Title (Invited Paper) Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits
Author Shuhan Zhang, *Fan Yang (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China)
Page pp. 440 - 445
Detailed information (abstract, keywords, etc)

 



Session 6D  (DF-2): Emerging Design
Time: 15:45 - 17:00 Wednesday, January 15, 2020
Location: Room 307B
Chair: Pingqiang Zhou (ShanghaiTech Univ.)

 

6D-1 (Time: 15:45 - 16:10)

Title (Designers' Forum) Recent Advances in Hardware Security and Testing Tools
Author Junfeng Fan (Open Security Research, Inc, China)
Detailed information (abstract, keywords, etc)

 

6D-2 (Time: 16:10 - 16:35)

Title (Designers' Forum) Design of Energy-Efficient Dynamic Reconfigurable Cryptographic Chip
Author Jinjiang Yang (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

 

6D-3 (Time: 16:35 - 17:00)

Title (Designers' Forum) Cognitive SSD Controller: A Case for Agile Domain-Specific SoC Design
Author Ying Wang (Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

 



Session 5K  Keynote Session V
Time: 17:30 - 18:10 Wednesday, January 15, 2020
Location: Room 311

 

5K-1 (Time: 17:30 - 18:10)

Title (Keynote Address) Emulation View of Synopsys Verification Continuum Platform
Author Michael Wang (Synopsys)
Detailed information (abstract, keywords, etc)

 


 

Thursday, January 16, 2020

 


Session 6K  Keynote Session VI
Time: 9:00 - 10:00 Thursday, January 16, 2020
Location: Room 311

 

6K-1 (Time: 9:00 - 10:00)

Title (Keynote Address) Explore the Next Tides of EDA
Author Lifeng Wu (Empyrean Software)
Detailed information (abstract, keywords, etc)

 



Session 7A  Neuromorphic Computing
Time: 10:15 - 11:30 Thursday, January 16, 2020
Location: Room 310
Chair: Shinya Takamaeda-Yamazaki (Univ. of Tokyo)

 

7A-1 (Time: 10:15 - 10:40)

Title Programmable Neuromorphic Circuit based on Printed Electrolyte-Gated Transistors
Author *Dennis D. Weller, Michael Hefenbrock, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany), Jasmin Aghassi-Hagmann (Offenburg Univ. of Applied Sciences, Germany), Michael Beigl (Karlsruhe Inst. of Tech., Germany)
Page pp. 446 - 451
Detailed information (abstract, keywords, etc)

 

7A-2 (Time: 10:40 - 11:05)

Title HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor
Author Shasha Guo, *Ziyang Kang, Lei Wang, Shiming Li, Weixia Xu (National Univ. of Defense Tech., China)
Page pp. 452 - 457
Detailed information (abstract, keywords, etc)

 

7A-3 (Time: 11:05 - 11:30)

Title A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation
Author *Yuki Kume, Song Bian, Takashi Sato (Kyoto Univ., Japan)
Page pp. 458 - 463
Detailed information (abstract, keywords, etc)

 



Session 7B  Machine Learning for Embedded Systems
Time: 10:15 - 11:30 Thursday, January 16, 2020
Location: Room 308
Chairs: Yongfu Li (Shanghai Jiao Tong Univ.), Huiyuan Song (Beijing Univ. of Tech.)

 

7B-1 (Time: 10:15 - 10:40)

Title MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition
Author *Qian Lou (Indiana Univ. Bloomington, USA), Wenyang Liu, Weichen Liu (Nanyang Technological Univ., Singapore), Feng Guo, Lei Jiang (Indiana Univ. Bloomington, USA)
Page pp. 464 - 469
Detailed information (abstract, keywords, etc)

 

7B-2 (Time: 10:40 - 11:05)

Title LanCe: A Comprehensive and Lightweight CNN Defense Methodology against Physical Adversarial Attacks on Embedded Multimedia Applications
Author *Zirui Xu, Fuxun Yu, Xiang Chen (George Mason Univ., USA)
Page pp. 470 - 475
Detailed information (abstract, keywords, etc)

 

7B-3 (Time: 11:05 - 11:30)

Title Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture
Author *Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan (Univ. of Texas, Austin, USA)
Page pp. 476 - 481
Detailed information (abstract, keywords, etc)

 



Session 7C  Malicious Activities Generation and Detection
Time: 10:15 - 11:30 Thursday, January 16, 2020
Location: Room 307A
Chairs: Xueyan Wang (Beihang Univ., China), Qiaoyan Yu (Univ. of New Hampshire, USA)

 

7C-1 (Time: 10:15 - 10:40)

Title Automated Trigger Activation by Repeated Maximal Clique Sampling
Author *Yangdi Lyu, Prabhat Mishra (Univ. of Florida, USA)
Page pp. 482 - 487
Detailed information (abstract, keywords, etc)

 

7C-2 (Time: 10:40 - 11:05)

Title Audio Adversarial Examples Generation with Recurrent Neural Networks
Author Kuei-Huan Chang, *Po-Hao Huang (National Tsing Hua Univ., Taiwan), Honggang Yu, Yier Jin (Univ. of Florida, USA), Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page pp. 488 - 493
Detailed information (abstract, keywords, etc)

 

7C-3 (Time: 11:05 - 11:30)

Title Database and Benchmark for Early-stage Malicious Activity Detection in 3D Printing
Author *Xiaolong Ma (Northeastern Univ., USA), Zhe Li (Syracuse Univ., USA), Hongjia Li (Northeastern Univ., USA), Qiyuan An (Virginia Polytechnic Inst. and State Univ., USA), Qinru Qiu (Syracuse Univ., USA), Wenyao Xu (State Univ. of New York, Buffalo, USA), Yanzhi Wang (Northeastern Univ., USA)
Page pp. 494 - 499
Detailed information (abstract, keywords, etc)

 



Session 7D  Embedded Software for Energy Optimization and Non-Volatile Memory
Time: 10:15 - 11:30 Thursday, January 16, 2020
Location: Room 307B
Chairs: Hussam Amrouch (Karlsruhe Inst. of Tech.), Sarah Bing Li (Capital Normal Univ.)

 

7D-1 (Time: 10:15 - 10:40)

Title EA-HRT: An Energy-Aware scheduler for Heterogeneous Real-Time systems
Author *Sanjay Moulik, Rishabh Chaudhary, Zinea Das (IIIT Guwahati, India), Arnab Sarkar (IIT Guwahati, India)
Page pp. 500 - 505
Detailed information (abstract, keywords, etc)

 

7D-2 (Time: 10:40 - 11:05)

Title Insights and Optimizations on IR-drop Induced Sneak-Path for RRAM Crossbar-based Convolutions
Author *Yujie Zhu, Xue Zhao, Keni Qiu (Capital Normal Univ., China)
Page pp. 506 - 511
Detailed information (abstract, keywords, etc)

 

7D-3 (Time: 11:05 - 11:30)

Title Boosting the Profitability of NVRAM-based Storage Devices via the Concept of Dual-Chunking Data Deduplication
Author *Shuo-Han Chen (Academia Sinica, Taiwan), Yu-Pei Liang (National Tsing Hua Univ., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan), Hsin-Wen Wei (Tamkang Univ., Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan)
Page pp. 512 - 517
Detailed information (abstract, keywords, etc)

 



Session 8A  Search and Optimization for Deep Neural Networks
Time: 13:50 - 15:30 Thursday, January 16, 2020
Location: Room 310
Chair: Li Jiang (Shanghai Jiao Tong Univ.)

 

8A-1 (Time: 13:50 - 14:15)

Title Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search
Author *Shulin Zeng, Hanbo Sun (Tsinghua Univ., China), Yu Xing (Tsinghua Univ., Xilinx, China), Xuefei Ning (Tsinghua Univ., China), Yi Shan (Xilinx, China), Xiaoming Chen (Chinese Academy of Sciences, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page pp. 518 - 523
Detailed information (abstract, keywords, etc)

 

8A-2 (Time: 14:15 - 14:40)

Title Search-free Accelerator for Sparse Convolutional Neural Networks
Author *Bosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li (Chinese Academy of Sciences, China)
Page pp. 524 - 529
Detailed information (abstract, keywords, etc)

 

8A-3 (Time: 14:40 - 15:05)

Title NESTA: Hamming Weight Compression-Based Neural Proc. Engine
Author Ali Mirzaeian, Houman Homayoun (George Mason Univ., USA), *Avesta Sasan (Institute for Research in Fundamental Sciences, USA)
Page pp. 530 - 537
Detailed information (abstract, keywords, etc)

 

8A-4 (Time: 15:05 - 15:30)

Title Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors
Author Baogang Zhang, Necati Uysal (Univ. of Central Florida, USA), Deliang Fan (Arizona State Univ., USA), *Rickard Ewetz (Univ. of Central Florida, USA)
Page pp. 538 - 543
Detailed information (abstract, keywords, etc)

 



Session 8B  FPGAs for Big Data Systems, Nonvolatile Computing, and Microfluidics
Time: 13:50 - 15:30 Thursday, January 16, 2020
Location: Room 308
Chairs: Tsun-Ming Tseng (Tech. Univ. of Munich, Germany), Xueqing Li (Tsinghua Univ., China)

 

8B-1 (Time: 13:50 - 14:15)

Title Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips
Author Zhanwei Zhong, Tung-Che Liang, *Krishnendu Chakrabarty (Duke Univ., USA)
Page pp. 544 - 549
Detailed information (abstract, keywords, etc)

 

8B-2 (Time: 14:15 - 14:40)

Title Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution
Author Satoru Maruyama (Ritsumeikan Univ., Japan), Debraj Kundu (Indian Inst. of Tech. Roorkee, India), *Shigeru Yamashita (Ritsumeikan Univ., Japan), Sudip Roy (Indian Inst. of Tech. Roorkee, India)
Page pp. 550 - 555
Detailed information (abstract, keywords, etc)

 

8B-3 (Time: 14:40 - 15:05)

Title An FPGA based Network Interface Card with Query Filter for Storage Nodes of Big Data Systems
Author Ying Li, *Jinyu Zhan, Wei Jiang, Junting Wu (Univ. of Electronic Science and Tech. of China, China), Jianping Zhu (Tencent Technology Shenzhen, China)
Page pp. 556 - 561
Detailed information (abstract, keywords, etc)

 

8B-4 (Time: 15:05 - 15:30)

Title Nonvolatile and Energy-Efficient FeFET-Based Multiplier for Energy-Harvesting Devices
Author *Mengyuan Li (Univ. of Notre Dame, USA), Xunzhao Yin (Zhejiang Univ., China), Xiaobo Sharon Hu (Univ. of Notre Dame, USA), Cheng Zhuo (Zhejiang Univ., China)
Page pp. 562 - 567
Detailed information (abstract, keywords, etc)

 



Session 8C  Advances in Logic/High-Level Synthesis
Time: 13:50 - 15:30 Thursday, January 16, 2020
Location: Room 307A
Chair: Bing Li (Tech. Univ. München)

 

8C-1 (Time: 13:50 - 14:15)

Title Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design
Author *Patrick Sittel (Univ. of Kassel, Germany), John Wickerson (Imperial College London, UK), Martin Kumm (Univ. of Applied Sciences Fulda, Germany), Peter Zipf (Univ. of Kassel, Germany)
Page pp. 568 - 573
Detailed information (abstract, keywords, etc)

 

8C-2 (Time: 14:15 - 14:40)

Title HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Author *Zhe Lin, Jieru Zhao (Hong Kong Univ. of Science and Tech., Hong Kong), Sharad Sinha (Indian Inst. of Tech. Goa, India), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong)
Page pp. 574 - 580
Detailed information (abstract, keywords, etc)

 

8C-3 (Time: 14:40 - 15:05)

Title DRiLLS: Deep Reinforcement Learning for Logic Synthesis
Author *Abdelrahman Hosny, Soheil Hashemi (Brown Univ., USA), Mohamed Shalan (American Univ. in Cairo, Egypt), Sherief Reda (Brown Univ., USA)
Page pp. 581 - 586
Detailed information (abstract, keywords, etc)

 

8C-4 (Time: 15:05 - 15:30)

Title Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization
Author *Jeongwoo Heo, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page pp. 587 - 592
Detailed information (abstract, keywords, etc)

 



Session 8D  Scalable and Reconfigurable Approximate Arithmetic Units
Time: 13:50 - 15:30 Thursday, January 16, 2020
Location: Room 307B
Chairs: Jie Han (Univ. of Alberta, Canada), Weikang Qian (Shanghai Jiao Tong Univ.)

 

8D-1 (Time: 13:50 - 14:15)

Title WEID: Worst-case Error Improvement in Approximate Dividers
Author *Hassaan Saadat (Univ. of New South Wales, Sydney, Australia), Haris Javaid (Xilinx, Singapore), Aleksandar Ignjatovic, Sri Parameswaran (Univ. of New South Wales, Sydney, Australia)
Page pp. 593 - 598
Detailed information (abstract, keywords, etc)

 

8D-2 (Time: 14:15 - 14:40)

Title Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules
Author *Yi Guo, Heming Sun, Shinji Kimura (Waseda Univ., Japan)
Page pp. 599 - 604
Detailed information (abstract, keywords, etc)

 

8D-3 (Time: 14:40 - 15:05)

Title LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy
Author *Zahra Ebrahimi, Salim Ullah, Akash Kumar (Tech. Univ. Dresden, Germany)
Page pp. 605 - 610
Detailed information (abstract, keywords, etc)

 

8D-4 (Time: 15:05 - 15:30)

Title Scaled Population Arithmetic for Efficient Stochastic Computing
Author *He Zhou, Sunil P. Khatri, Jiang Hu (Texas A&M Univ., USA), Frank Liu (IBM Research, USA)
Page pp. 611 - 616
Detailed information (abstract, keywords, etc)

 



Session 9A  (SS-5): Resilience in Integrated Systems
Time: 15:45 - 17:00 Thursday, January 16, 2020
Location: Room 310
Chair: Masanori Hashimoto (Osaka Univ., Japan)

 

9A-1 (Time: 15:45 - 16:10)

Title (Invited Paper) Soft Error and Its Countermeasures in Terrestrial Environment
Author *Masanori Hashimoto (Osaka Univ., Japan), Wang Liao (Kochi Univ. of Tech., Japan)
Page pp. 617 - 622
Detailed information (abstract, keywords, etc)

 

9A-2 (Time: 16:10 - 16:35)

Title (Invited Paper) Timing Resilience for Efficient and Secure Circuits
Author Grace Li Zhang, Michaela Brunner, *Bing Li, Georg Sigl, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page pp. 623 - 628
Detailed information (abstract, keywords, etc)

 

9A-3 (Time: 16:35 - 17:00)

Title (Invited Paper) Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems
Author Jürgen Teich, Behnaz Pourmohseni, *Oliver Keszocze, Jan Spieck, Stefan Wildermann (Friedrich-Alexander-Univ. Erlangen-Nürnberg (FAU), Germany)
Page pp. 629 - 636
Detailed information (abstract, keywords, etc)

 



Session 9B  (SS-6): Emerging Technologies across the Abstraction Layers
Time: 15:45 - 17:00 Thursday, January 16, 2020
Location: Room 308
Chair: Hussam Amrouch (Karlsruhe Inst. of Tech. (KIT), Germany)

 

9B-1 (Time: 15:45 - 16:10)

Title (Invited Paper) NCFET to Rescue Technology Scaling: Opportunities and Challenges
Author *Hussam Amrouch, Victor M. van Santen (Karlsruhe Inst. of Tech., Germany), Girish Pahwa (Indian Inst. of Tech. Kanpur, India), Yogesh Chauhan (Indian Inst. of Tech. Kanpur, Germany), Jörg Henkel (Karlsruhe Inst. of Tech. (KIT), Germany)
Page pp. 637 - 644
Detailed information (abstract, keywords, etc)

 

9B-2 (Time: 16:10 - 16:35)

Title (Invited Paper) Parallelism in Deep Learning Accelerators
Author *Linghao Song, Fan Chen, Yiran Chen, Hai (Helen) Li (Duke Univ., USA)
Page pp. 645 - 650
Detailed information (abstract, keywords, etc)

 

9B-3 (Time: 16:35 - 17:00)

Title (Invited Paper) Software-Based Memory Analysis Environments for In-Memory Wear-Leveling
Author *Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Blömeke, Jian-Jia Chen (TU Dortmund, Germany)
Page pp. 651 - 658
Detailed information (abstract, keywords, etc)

 



Session 9C  (SS-7): CMOS Annealing Hardware: Pursuing Efficiency for Solving Combinatorial Optimization Problems
Time: 15:45 - 17:00 Thursday, January 16, 2020
Location: Room 307A
Chair: Shu Tanaka (Waseda Univ., Japan)

 

9C-1 (Time: 15:45 - 16:10)

Title (Invited Paper) Theory of Ising Machines and a Common Software Platform for Ising Machines
Author *Shu Tanaka (Waseda Univ., Japan), Yoshiki Matsuda (Fixstars, Japan), Nozomu Togawa (Waseda Univ., Japan)
Page pp. 659 - 666
Detailed information (abstract, keywords, etc)

 

9C-2 (Time: 16:10 - 16:35)

Title (Invited Paper) Digital Annealer for High-Speed Solving of Combinatorial Optimization Problems and Its Applications
Author *Satoshi Matsubara, Motomu Takatsu, Toshiyuki Miyazawa, Takayuki Shibasaki, Yasuhiro Watanabe, Kazuya Takemoto, Hirotaka Tamura (Fujitsu Labs., Japan)
Page pp. 667 - 672
Detailed information (abstract, keywords, etc)

 

9C-3 (Time: 16:35 - 17:00)

Title (Invited Paper) CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem
Author *Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka (Hitachi, Japan)
Page pp. 673 - 678
Detailed information (abstract, keywords, etc)

 



Session 9D  (DF-3): AI Accelerators
Time: 15:45 - 17:00 Thursday, January 16, 2020
Location: Room 307B
Chair: Xiaoming Chen (Chinese Academy of Sciences)

 

9D-1 (Time: 15:45 - 16:10)

Title (Designers' Forum) AI Chips, What's Next: Architecture, Tools, and Methodology
Author Shan Tang (AI chip expert, China)
Detailed information (abstract, keywords, etc)

 

9D-2 (Time: 16:10 - 16:35)

Title (Designers' Forum) Computing-in-Memory SoC Chip for Neural Network Inference
Author Shaodi Wang (Witin Tech, China)
Detailed information (abstract, keywords, etc)

 

9D-3 (Time: 16:35 - 17:00)

Title (Designers' Forum) Enabling Data Center-Wide Accelerator Resource Pools for AI Applications
Author Kun Wang (VirtAI Tech, China)
Detailed information (abstract, keywords, etc)