2023 28th Asia and South Pacific Design Automation Conference ASP-DAC

活动简介

ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2023 is 28th conference. ASP-DAC 2023 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers' Forum to make presentations about the latest designs for designers. Please do not miss ASP-DAC 2023.

组委会

General Chair

Atsushi Takahashi (Tokyo Institute of Technology)

Past Chair

Ting-Chi Wang (National Tsing Hua University)

GC Secretaries

Kazuyuki Iwaguro (Renesas Electronics Corporation)

Shimpei Sato (Shinshu University)

Yukihide Kohira (The University of Aizu)

GC Advisor

Tohru Ishihara (Nagoya University)

Technical Program Chair

Gi-Joon Nam (IBM Research)

TPC Vice Chair

Iris Hui-Ru Jiang (National Taiwan University)

Masanori Hashimoto (Kyoto University)

Tutorial Co-Chairs

Yasuhiro Takashima (The University of Kitakyushu)

Takahide Yoshikawa (Fujitsu Laboratories)

Design Contest Co-Chairs

Akira Tsuchiya (The University of Shiga Prefecture)

Mahfuzul Islam (Kyoto University)

Designer's Forum Co-Chairs

Koichiro Yamashita (Fujitsu R&D Center)

Takatsugu Ono (Kyushu University)

Finance Co-Chairs

Kenshu Seto (Tokyo City University)

Hiroyuki Tomiyama (Ritsumeikan University)

Publication Co-Chairs

Kohei Miyase (Kyushu Institute of Technology)

Shinobu Nagayama (Hiroshima City University)

Publicity Co-Chairs

Nozomu Togawa (Waseda University)

Daisuke Kumamoto (Renesas Electronics Corporation)

Kazushi Kawamura (Tokyo Institute of Technology)

Web Publicity Co-Chairs

Jun Shiomi (Osaka University)

Yutaka Masuda (Nagoya University)

Promotion Co-Chairs

Matthieu Parizy (Fujitsu Laboratories)

Takashi Takenaka (NEC)

Atsuhiro Suga (Socionext)

ASP-DAC Liaison at ACM SIGDA Student Research Forum

Masashi Tawada (Waseda University)

Shinichi Nishizawa (Waseda University)

Secretariat

Koji Sugawara (PCO Works)

Yingran XU (PCO Works)

征稿信息

重要日期

2022-07-24

摘要截稿日期

2022-09-10

摘要录用日期

2022-11-04

终稿截稿日期

ASP-DAC 2023 is the 28th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.

征稿范围

Areas of Interest:
Original papers in, but not limited to, the following areas are invited.

1 System-Level Modeling and Design Methodology:
1.1. HW/SW co-design, co-simulation and co-verification
1.2. System-level design exploration, synthesis, and optimization
1.3. System-level formal verification
1.4. System-level modeling, simulation and validation
1.5. Networks-on-chip and NoC-based system design

2 Embedded, Cyberphysical (CSP) and IoT Systems:
2.1. Many- and multi-core SoC architecture
2.2. IP/platform-based SoC design
2.3. Domain-specific architecture
2.4. Dependable architecture
2.5. Cyber physical system
2.6. Internet of things

3 Embedded Systems Software:
3.1. Kernel, middleware, and virtual machine
3.2. Compiler and toolchain
3.3. Real-time system
3.4. Resource allocation for heterogeneous computing platform
3.5. Storage software and application
3.6. Human-computer interface

4 Memory Architecture and Near/In Memory Computing:
4.1. Storage system and memory architecture
4.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
4.3. Memory/storage hierarchies with emerging memory technologies
4.4. Near-memory and in-memory computing
4.5. Memory architecture and management for emerging memory technologies

5 AI/Machine Learning Circuits, Architecture, System Designs and Applications:
5.1. Hardware and devices for deep neural networks
5.2. Design method for learning on a chip
5.3. Systems and design methods for deep neural computing
5.4. Neural network acceleration co-design techniques
5.5. Design techniques for AI of Things
5.6. Novel reconfigurable architectures including FPGAs for AI/MLs
5.7. Efficient ML training and inference

6 Photonic/RF/Analog-Mixed Signal Design:
6.1. Analog/mixed-signal/RF synthesis
6.2. Analog layout, verification, and simulation techniques
6.3. High-frequency electromagnetic simulation of circuit
6.4. Mixed-signal design consideration
6.5. Communication and computing using photonics

7 Approximate, Bio-Inspired and Neuromorphic Computing:
7.1. Circuit and system techniques for approximate and stochastic computing
7.2. Neuromorphic computing
7.3. CAD for approximate and stochastic systems
7.4. CAD for bio-inspired and neuromorphic systems

8 High-Level, Behavioral, and Logic Synthesis and Optimization:
8.1. High-level/Behavioral synthesis tool and methodology
8.2. Combinational, sequential and asynchronous logic synthesis
8.3. Technology mapping, resource scheduling, allocation and synthesis
8.4. Functional and logic timing ECO (Engineering change order)
8.5. Interaction between logic synthesis and physical design

9 Physical Design and Timing Analysis:
9.1. Floorplanning, partitioning and placement and routing optimization
9.2. Interconnect planning and synthesis
9.3. Clock network synthesis
9.4. Post layout and post-silicon optimization
9.5. Package/PCB/3D-IC routing
9.6. Extraction, TSV and package modeling
9.7. Deterministic/statistical timing analysis and optimization
9.8. Signal/Power integrity, EM modeling and analysis

10 Design for Manufacturability/Reliability and Low Power:
10.1. Reticle enhancement, lithography-related design and optimization
10.2. Resilience under manufacturing variation
10.3. Design for manufacturability, yield, and defect tolerance
10.4. Reliability, robustness, aging and soft error analysis
10.5. Power modeling, analysis and simulation
10.6. Low-power design and optimization at circuit and system levels
10.7. Thermal aware design and dynamic thermal management
10.8. Energy harvesting and battery management

11 Testing, Validation, Simulation, and Verification:
11.1. ATPG, BIST and DFT
11.2. System test and 3D IC test, Online test and fault tolerance
11.3. Memory test and repair
11.4. RTL and gate-leveling modeling, simulation, and verification
11.5. Circuit-level formal verification
11.6. Device/circuit-level simulation tool and methodology

12 Hardware and Embedded Security:
12.1. Hardware-based security
12.2. Detection and prevention of hardware Trojans
12.3. Side-channel attacks, fault attacks and countermeasures
12.4. Design and CAD for security
12.5. Cyberphysical system security
12.6. Nanoelectronic security
12.7. Supply chain security and anti-counterfeiting

13 Emerging Devices, Technologies and Applications:
13.1. Quantum and Ising computing
13.2. Nanotechnology, MEMS
13.3. Biomedical, biochip, and biodata processing
13.4. Edge, fog and cloud computing
13.5. Energy-storage/smart-grid/smart-building design and optimization
13.6. Automotive system design and optimization
13.7. New transistor/device and process technology: spintronic, phase-change, single-electron etc

作者指南

ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals. The submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, references and bibliographic citations. While research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar), the authors' identities need to be anonymized in the submitted paper for the double-blind review process. Issuing the paper as a technical report, posting the paper on a website, or presenting the paper at a workshop that does not publish formally reviewed proceedings, does not disqualify it from appearing in the proceedings. Note that each paper shall be accompanied by at least one different conference registration at the speaker's registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by any author.