• Being held biannually.
• 100-200 papers were submitted every two years, totally over 1500 papers were submitted between
> Focusing on process and advanced technology.
> With oral presentations and short courses.
> Focusing on design, design automation, and testing.
> With oral presentations, poster presentations, and tutorials.
• More than 4500 attendees attended the VLSI-TSA and DAT symposia.
The cocktail reception for symposia ( VLSI-TSA and VLSI-DAT ) will be held on Tuesday, April 23 from 6:30 P.M. to 8:30 P.M. One admission to the reception is included in the registration fee. Welcome all participants and their spouses join us.
* The Conference Badge is required for the entry of all the events during the 2019 VLSI-TSA and DAT. *
peaker 1: Li Fung Chang, Industrial Technology Research Institute, Taiwan
Topic : Journey to 5G
• Speaker 2: Peter Hsieh, ARM, Taiwan, Taiwan
Topic : VLSI Design for Autonomous Driving System
• Speaker 3: Mike Davies, Intel, USA
Topic : TBD
More information will coming soon.....
We appreciate your interest in submitting a paper to the 2019 International Symposium on VLSI Design, Automation, and Test (2019 VLSI-DAT). Herewith forms and information are provided for your preparation of paper submission.
• Prospective authors must submit a self-contained paper with figures and tables electronically through the conference website by Oct.31, 2018 (23:59 GMT+8)
• The length of a submitted paper must be 2-4 pages. Any submissions not adhering to the length constraint will be returned immediately without review.
• In addition to the paper and camera-ready manuscript, the submission should be included with a 80~100 Word ABSTRACT, which will be published in the advance and final program if the paper is accepted.
• VLSI-DAT adopts the DOUBLE BLIND REVIEW process; please DO NOT reveal your name(s) or affiliation(s) anywhere in the submitted manuscript for the first paper submission.
• Before submitting your abstract/paper, please review the information on IEEE Intellectual Property Rights at http://www.ieee.org/web/publications/rights/index.html
• The notices of acceptance will be sent out to authors on December 28, 2018.
• Any changes on title and author list or withdraw after acceptance must be approved by Technical Program Co-Chairs.
• For an accepted paper to be published in the proceedings, one of its co-author(s) MUST pay the full registration fee by February 28, 2019 23:59 (GMT+8) and attend the symposium to present the paper. Note that each accepted paper shall be accompanied by a different full registration; that is, two full registrations are required for presenting two papers even if the presenter is the same.
• Presentation of accepted papers at the symposium must be in English and will be limited to 18 minutes with an additional 2 minutes for Q&A. The final manuscript of all accepted papers will be published as submitted in the proceedings.
• No-show papers will not be included in the symposium proceedings and will not be submitted to the IEEE Xplore database.
Two best papers will be selected this year through a rigorous evaluation process, which is conducted by the program committee and session chairs.
Original, unpublished papers on all aspects of VLSI Design, Automation and Test are solicited, including but not limited to:
|ANALOG DESIGN||DIGITAL DESIGN||EDA||TEST|
|RF, Analog and Mixed Signal Circuits||Digital Circuits and ASICs||Logic and Behavioral Synthesis||Test Generation and Compression|
|Sensors and Interface Circuits||CPU, DSP and Multicore Architectures||Physical Design and Verification||Design-for-Testabilityand BIST|
|Memory Circuits and Systems||Multimedia Processing Designs||Design for Manufacturability||RF, Analog and Mixed-Signal Test|
|Biomedical Circuits||Communication Designs||Power/Thermal Estimation and Optimization||Memory Test|
|Energy-Harvesting and Power Circuits||Hardware Security and Trust||Design Verification||SOC and System Level Test|
|Ultra Low-Power Circuits and Systems||Designs for Edge Computing||Modeling and Simulation||Silicon Debug and Diagnosis|
|Memristive and Neuromorphic Circuits||Designs for Machine Learning||Electronic System Level Design||3D IC and Interposer-Based IC Test|
|Security Circuits for IoT and AI||SOC and NOC Architectures||Hardware/Software Co-Design||Yield and Reliability Enhancement|
|Embedded System and Software||Machine Learning for EDA||On-Chip Monitoring|
|System-in-Package Designs||Analog EDA||Test Data Mining and Learning|
|EDA for Microfluidic Biochips||Test Standards|
• Tim Cheng, Hong Kong University of Science and Technology (HKUST), Hong Kong
• Tzi-Cker Chiueh, Industrial Technology Research Institute, Taiwan
• Tzi-Dar Chiueh, National Taiwan University, Taiwan
• Jiun-In Guo, National Chiao Tung University, Taiwan
• Shye-Jye Jou, National Chiao Tung University, Taiwan
• Kuen-Jong Lee, National Cheng Kung University, Taiwan
• Donald Y.C. Lie, Texas Tech. University, USA
• Youn-Long Lin, National Tsing Hua University, Taiwan
• Jyuo-Min Shyu, National Tsing Hua University, Taiwan
• Li-C. Wang, University of California Santa Barbara, USA
• Cheng-Wen Wu, National Tsing Hua University, Taiwan