You are invited to submit an abstract, presenting new development in the following categories: Advanced Packaging: Flip-chip and wire-bond packaging, embedded passives and actives on substrates, 3D System in Packaging, etc. TSV/Wafer Level Packaging: Wafer level packaging, embedded chip packaging, 2.5D/3D integration, TSV, Silicon interposer, RDL, bumping technologies, etc. Interconnection Technologies: Wire-bondtechnology, Flip-chip technology, solderalternatives (ICP, ACP, ACF, NCP), die attachment (Pb-free), etc. Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc. Materials & Processes: Materials and processes for traditional and advanced microelectronic systems, MEMS, solar, green and biomedical packaging. Electrical Modeling & Simulations: Power plane modeling, signal integrity analysis of substrate/package. Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, and drop impact modeling, Chip-package interaction, etc. Thermal Characterization & Cooling Solutions: Thermal modeling and simulation, component and system level thermal management and characterization Quality & Reliability: Component, board and system level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc. Wafer/Package Testing & Characterization: High-speed test architectures and systems design, test methodologies, probe card design, package-test interaction, high-throughput testing etc.