After a very successful first edition in 2013, the 2014 second edition of the IEEE S3S will take place in San Francisco, CA. IEEE S3S is the combination of the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. This industry-wide event will gather together widely known experts, contributed papers and invited talks on 3 main topics: (1) SOI Technology, (2) Subthreshold circuit designs, architectures, and devices, and (3) 3D Integration. Combining these three topics enables us to provide very extensive and high quality technical content, and makes the conference the perfect venue to present and learn about the most up to date trends in CMOS and post-CMOS Scaling and the low-power SOC eco-system. The IEEE S3S organizers are pleased to welcome you to this exciting event, which allows attendees to access essentially three conferences with one registration fee. This year our conference will host parallel tracks for the SOI and Subthreshold Microelectronics. In addition, we will be again be featuring 3D Integration. The technical sessions will be preceded by two one-day Tutorial Short Courses highlighting exciting opportunities and their implication in CMOS scaling. We will also be offering two Fundamental Classes as well this year.