2021 IEEE International Conference on Networking, Architecture and Storage NAS

活动简介

The 15th International Conference on Networking, Architecture, and Storage (NAS 2021) will be held at Riverside, CA. NAS provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2021 will expose participants to the most recent developments in the interdisciplinary areas.

Sponsor Type:1

组委会

Network Track

Track Chairs

- Yan Luo Univ. Mass. Lowell

Program Committee

- Hongxin Hu, Clemson University
- Liyao Xiang, Shanghai Jiaotong University
- Guangdeng Liao, Facebook
- Peilong Li, Elizabethtown College
- Deng Pan, Florida International University
- Jay N. Bhuyan, Tuskegee University
- Anu Merican, HPE
- Nathan Hanford, Lawrence Livermore National Lab
- Xiaohong Jiang, Future University Hakodate, JP
- Mariam Kiran, Lawrence Berkeley National Laboratory
- Alexander Sim, Lawrence Berkeley National Laboratory
- Cody Bumgardner, University of Kentucky
- Xiaoban Wu, Juniper
- Haojun Huang, Huazhong Univ of Science and Tech
- Tong Zhang, Intel Corporation
- Liang-min Wang, Intel Corporation
- Viswanath Ramamurthi, Verizon Labs
- K. K. Ramakrishnan, UC Riverside
- Satya Mohanty, Cisco
- Bin Liu, Tsinghua Univ.
- James Griffioen, Univ. of Kentucky

Architecture Track

Track Chair

- E.J. Kim, Texas A&M

Program Committee

-Mehmet Belviranli, Colorado School of Mines
-Yeimkuan Chang, National Cheng-kung University
-Lizong Chen, Oregon State University
-Reetuparna Das, University of Michigan
-Jiayi Huang, Texas A&M University
-Yuho Jin, AMD Research
-Adwait Jog, College of William & Mary
-Myoungsoo Jung, Yonsei University
-Onur Kayiran, AMD Research
-Aasheesh Kolli, Penn State
-Asit Mishra, Nvidia
-Ashutosh Pattnaik, ARM
-Bikash Sharma
-Xulong Tang, University of Pittsburgh
-Nian-Feng Tzeng, University of Louisiana
-Prasanna Venkatesh, Apple
-Hong Wang, Intel
-Daniel Wong, University of California, Riverside
-Fan Yao, University of Central Florida

Storage Track

Track Chair

- Yifeng Zhu, University of Maine

Program Committee

- Ahmed Amer, Santa Clara University
- Andre Brinkmann, University of Mainz, Germany
- Ali R. Butt, AVirginia Tech
- Qiang Cao, HUST, China
- Song Jiang, UTA, USA
- Myoungsoo Jung, KAIST, Korea
- Adam Manzanaares, HGST, Western Digital
- Yijun Lu, Alibaba, China
- Youyou Lu, Tsinghua, China
- Xiao Qin, Auburn University
- Pradeep Subedi, Rutgers
- Zili Shao, Chinese Univ. of Hong Kong
- Philip Shilane, Dell-EMC
- Hui Tian, Huaqiao Univ., China
- Lei Tian, Facebook
- Devesh Tiwari, Northeastern
- Peter Varman, Rice Univ.
- Qingsong Wei, A-Star, Singapore
- Chentao Wu, Shanghai Jiao Tong University
- Tao Xie, San Diego State Univ.
- Wen Xia, Harbin Inst. of Tech., China
- Jason Xue, City Univ. of Hong Kong
- Zhichao Yan, HPE
- Shu Yin, Shanghai Tech University
- Ziliang Zong, Texas State Univ.
- Yi Zou, Intel
- Xunfei Jiang, California State Univ., Northridge

征稿信息

征稿范围

Topics of interest include, but are not limited to the following:

- Accelerator-based architectures
- Ad hoc and sensor networks
- Application-specific, reconfigurable or embedded architectures
- Architecture for handheld or mobile devices
- Architecture, networking or storage modeling and simulation methodologies
- Big Data infrastructure
- Big Data services and analytics
- Cloud and grid computing
- Cloud storage
- Data-center scale architectures
- Effects of circuits and emerging technology on architecture
- Energy-aware storage
- File systems, object-based storage
- GPU architecture and programming
- HW/SW co-design and tradeoffs
- Mobile and wireless networks
- Network applications and services
- Network architecture and protocols
- Network information theory
- Network modeling and measurement
- Network security
- Non-volatile memory technologies
- Parallel and multi-core architectures
- Parallel I/O
- Power and energy efficient architectures and techniques
- Processor, cache, memory system architectures
- Software defined networking
- Software defined storage
- SSD architecture and applications
- Storage management
- Storage performance and scalability
- Storage virtualization and security
- Virtual and overlay networks

作者指南

Each submission can have up to 8 pages, including all text, figures, tables, footnotes, appendices, references, etc. Authors are invited to submit previously unpublished work for possible presentation at the conference. The program committee will nominate best papers for recognition in the three conference topic areas. All papers will be evaluated based on their novelty, fundamental insight, experimental evaluation, and potential for long-term impact; new-idea papers are encouraged. All accepted papers will be published in IEEE digital library. Selected and extended papers will be recommended for journal publications.