The session will cover the new trends in Reconfigurable Logic Design and Verification, including the new techniques of partitioning big deigns on single or multiple FPGAs, the use of the reconfigurable logic to implement complex designs, the use of FPGAs as accelerators, NoC and Security-aware design implementation on FPGA and secure Furthermore, the session will cover design verification using Emulators and FPGA-based prototyping. Finally, it will address the use of the virtual prototyping approach combined with emulation and FPGA verification methodologies.