Many-core architectures, such as mobile SOCs, GPGPUs, and deep learning accelerators, are quickly becoming the norm in computing devices and consumer electronics. In the era of dark silicon, this is essential for sustaining performance growth in an energy efficient way. Still, there is no consensus on how software can make best use of it. Developing parallel applications often starts with an existing sequential implementation. A key problem is how to discover the parallelism potentially available and then convert it into a form that can be exploited. Once we have a parallel implementation, its performance and energy efficiency largely depend on how it is mapped to the available hardware. Given that hardware is increasingly diverse and heterogeneous and that, due to dark silicon, energy efficiency affects the availability of hardware, how can this re-mapping be best achieved. Solutions to these two problems form the core topic of the workshop.