As HPC applications scale to large supercomputing systems, their communication and synchronization need to be optimized in order to deliver high performance. To achieve this, capabilities of modern network interconnect and parallel runtime systems need to be advanced and the existing ones to be leveraged optimally. The workshop will bring together researchers and developers to present and discuss work on optimizing communication and synchronization in HPC applications. This includes, but is not limited to, methodological and algorithmic advances in topology-aware or topology-oblivious blocking and non-blocking collective algorithms, offloading of communication to network interface cards, topology aware process mappings for minimizing communication overhead on different network topologies such as dragonfly, high-dimensional torus networks, fat trees, optimizations for persistent communication patterns, studies and solutions for inter-job network interference, overlapping of communication with computation, optimizing communication overhead in presence of process imbalance, static or runtime tuning of collective operations, scalable communication endpoints for manycore architectures, network congestion studies and mitigation methods, communication optimizations on peta/exa-scale systems, heterogeneous systems, and GPUs, machine learning to optimize communication, and communication aspects of GPGPU, graph applications, or fault tolerance. The workshop also aims at bringing researchers together to foster discussion, collaboration, and ideas for optimizing communication and synchronization that drive design of future peta/exascale systems and of HPC applications. In addition, we expect that researchers and others looking for research directions in this area will get up-to-date with the state-of-the-art so that they can drive their research in a manner that will impact the future of HPC.