Signal processing beyond performance optimization. Future signal processing applications will have to consider processing latency and power constraints in addition to pursuing optimal system performance. The fundamental dilemma is that the complexity of SP is rapidly increasing to improve system performance while target data-rate of real applications increase exponentially. For example, Ethernet system increases 10x speed every 8 years. Thus we face power, area, and/or latency constrained performance optimization for Signal Processing in the future especially when we target at multi-Gbps and beyond applications.
VLSI Based Design and Implementation of Signal Processing Systems
Low-power signal processing circuits and applications
High performance VLSI systems
VLSI design for 100 Gbps and beyond networking systems
FPGA and reconfigurable architecture based systems
System-on-chip and network-on-chip
VLSI Systems for Wireless Sensor Network and RF Identification Systems
Software Based Design and Implementation of Signal Processing Systems
Programmable digital signal processor architecture and systems
Application specific instruction-set processor (ASIP) architecture and systems
SIMD, VLIW and multi-core CPU architecture
Graphic processing unit (GPU) based massively parallel implementation
Embedded FPGA architectures
Design Methods of Signal Processing Algorithms and Architectures
Optimization of signal processing algorithms
Compilers and tools for signal processing systems
Algorithm transformation and algorithm-to-architecture mapping
Error-Tolerant Techniques for Signal Processing
Signal Processing Application Systems
Audio, speech and language processing
Biomedical signal processing and bioinformatics
Image, video and multimedia signal processing
Information forensics, security and cryptography
Machine learning for signal processing
Sensing and sensor signal processing
Autonomous energy harvesting-based sensor networks
Signal processing for non-volatile memory systems
Latency and power constrained signal processing techniques for high-speed networking
Wireless communications and networking
Coding and Compression
Multiple-Input-Multiple-Output (MIMO) and Communication Systems
Software Defined Radio
Emerging Technologies
Vehicular ad hoc networks (VANET)
Cognitive radio networks
Internet of Things (IoT)
Deep learning and reconfigurable/ASIC processors
Bio-inspired networks
Context-aware mobile networking
Wireless body area networks (WBANs)
Implantable Communications
Tele-medicine/e-health networks
Signal Processing Compensation Techniques for Analog and Digital VLSI
Digital Compensation techniques for variations in Silicon process, temperature, aging
Error Detection and Correction for Volatile and Non Volatile Memories
Power Reduction and SNR Improvement for On-chip and off-chip interconnects and buses
Digital Compensation Signal Processing for ADCs, power-amps, MEMS, power Controllers
10月26日
2016
10月28日
2016
初稿截稿日期
初稿录用通知日期
终稿截稿日期
注册截止日期
2018年10月21日 南非
2018 IEEE International Workshop on Signal Processing Systems2017年10月03日 法国 Lorient
2017 IEEE International Workshop on Signal Processing Systems
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