第六届国际众核时代新算法和编程模型研讨会 The 6th International Workshop on New Algorithms and Programming Models for the Manycore Era APMM 2016

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活动简介

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance. In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, Intel SCC, integrated GPUs etc.) add further challenges to efficient programming in HPC applications.

Therefore, compute and data intensive tasks can only benefit from the hardware's full potential, if both processor and architecture features are taken into account at all stages - from the early algorithmic design, via appropriate programming models, up to the final implementation.

征稿信息

重要日期

2016-04-14

初稿截稿日期

2016-04-28

初稿录用日期

2016-05-21

终稿截稿日期

征稿范围

The APMM Workshop topics of interest include (but are not limited to) the following:

Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).
Manycore-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.
Parallelisation on HPC platforms; esp. platforms with hierarchical communication layout, multi-/many-core platforms, NUMA architectures, or accelerator components (Intel Xeon Phi, NVIDIA and AMD GPU, Tilera, FPGA, integrated GPUs (such as AMD APUs or Intel Haswell/Ivy Bridge)).
Parallelisation with appropriate programming models and tool support for multi-core and hybrid platforms.
concepts for exploiting emerging vector extensions of instruction sets
Software engineering, code optimisation, and code generation strategies for parallel systems with multi-core processors.
Tools for performance and cache behavior analysis (including cache simulation) for parallel systems with multi-core processors.
Performance modelling and performance engineering approaches for multi-thread and mutli-process applications.

作者指南

You are invited to submit original and unpublished research works on above and other topics related to Many-core computing. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.

Submit a PDF copy of your full manuscript to the workshop paper submission EasyChair site at xxx. Acknowledgement will be sent within 48 hours of submission.

Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2016 conference to present the paper at the workshop.