The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-third in the TAU series, the TAU 2016 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below.

Timing (including incremental timing)

· System/circuit-level timing

· Gate/transistor-level timing

· Timing of mixed signal circuits, FPGAs

· New types of latches, dual-edge devices, etc.

· Distributed timing analysis Modeling and simulation

· Transistor level modeling

· Analog circuit modeling

· Circuit level simulation

· Delay models and metrics

· Aging, reliability modeling and simulation

Variability

· Timing analysis under uncertainty

· Ultra-low voltage induced variation effects

· Statistical timing analysis and optimization

· Sensitivity/criticality analysis

· Yield analysis and optimization

Power, trade-offs and optimization

· Timing issues in low-power design

· Power-delay tradeoffs

· Layout impact on timing

· Timing driven layout optimization

· Timing driven synthesis, re-synthesis

· Circuit optimization Signal integrity

· Crosstalk modeling, analysis, avoidance and optimization

· Noise and glitch analysis

· Variation-aware

signal integrity analysis Clocking

· Complex clock trees and networks

· Clocking, synchronization, and skew

· Clock domains, static/dynamic logic

· Novel clocking schemes Characterization

· Cell (library) characterization

· Variation effects and corner reductions

· Latch characterization

· Simulation and characterization of SRAM circuits Hierarchical timing

· Timing macro-modeling: timing, SI, power, etc.

· Hierarchical optimization and sign-off

· Integration/Interoperation with implementation flow Emerging technologies

· Full custom design analysis

· Smart sensor placement

· Timing issues for 3D ICs, TSVs

· Timing implications of emerging technologies Others

· Integrated functional-temporal analysis

· Formal theories and methods

· Asynchronous systems

· Localization and debug of timing errors