Scalable interconnect architectures form the solid base on top of which future complex computing platforms will be developed. The interconnect architecture should be as high performance as its connecting nodes, thus enabling the expected exponential growth in system concurrency. The number of nodes either on-chip or off-chip that need to communicate in modern embedded and HPC systems is constantly increasing. This trend poses significant challenges to the interconnection network designers that tackle a multidimensional problem involving hardware and software components such as network interfaces, switches, and communication library APIs.

At the same time, new usage models of mobile devices together with the digital convergence trend require that largely different operating conditions are accommodated by a single, deeply reconfigurable design. In this direction, heterogeneity could take the form of runtime specialization rather than design time customization. Similarly, manufacturing yield and device availability could be significantly improved by the device capability to adapt to hardly predictable and even changing operating conditions at runtime.

With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as the primary concerns for scalable computing. To achieve viable high performance, revolutionary methods are required with a stronger integration among hardware features, system software and applications.

A main purpose of this workshop is to promote further research interests and activities on Silicon Photonics and related topics in the perspective of its adoption in future high performance systems and, in general, within future computing systems (from servers/workstations down to embedded devices). In fact, Silicon Photonics poses in itself crucial challenges and interesting design tradeoffs for being deployed in future computer systems effectively, also in integration with other technologies. Furthermore, the unique features of photonics (e.g. extreme low-latency, end-to-end transmission, high bandwidth density) have the potential to constitute a discontinuity element able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives.

The AISTECS workshop aims to increase the synergy from a complete range of viewpoints, from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems, both from academic and industrial researchers working in this area. We are interested in experimental, systems-related, and work-in-progress papers in all aspects of interconnects in general and SiP technology in particular at all levels of development.