Submission Topics Dynamic compilation and architectural interaction: Just-In-Time compilation: efficiency, persistence, ahead-of-time compilation Efficient bytecode translation issues Efficient ISA representation for dynamic compilation Efficient compilation methods Binary translation: Architectural effects and experience: Novel applications of binary translation and virtualization Performance characterization Dynamic instrumentation and debugging HW/SW co-design for efficient execution Experimental insights and industrial experience Hardware assistance for optimization: Extra/enhanced internal/physical registers Speculative execution support Reduced footprint/low-power cores enabled by binary translation, area and power efficiency Techniques for parallelizing single-threaded programs Hardware assistance for translation and code discovery: Interpretation, decoding assistance, code dispatch On-the-fly reconstruction of CFGs, data dependences, scheduling and optimization Bug-per-bug compatibility issues Static and hybrid (runtime-assisted) translation Binary translation: Heterogeneous cores and applications: Dynamic code targeting heterogeneous architectures Dynamic parallelization, vectorization Power-efficient execution CPU-GPU code migration Novel architectures, memory systems and caching for CPU/GPU Hardware assistance for runtime management: Self-modifying/self-referential code, precise exceptions Runtime profiling: branches, caches, memory accesses Management of translated code Adapting code to changing program behavior Persistent translation, incremental translation Parallel translation, auto parallelization, speculation