Many-core embedded systems (MES) are moving towards the integration of hundreds of cores on a single chip and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication becomes a power and performance bottleneck in future MESs. Networks-on-Chip (NoC) have has been proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoCs provide an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications using the full power of NoC-based MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that, contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing scalable and fault-tolerant OSs will be a tremendous challenge in future MESs. In addition, as neuromorphic and mixed-signal architectures are emerging as an alternative solution beyond the conventional digital von Neumann machines for complex applications, we would like to highlight such emerging architectures in this workshop.