活动简介

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

组委会

General Chairs

Prashant Joshi    Intel, United States    prashant.d.joshi@intel.com
Luigi Dilillo    LIRMM, France    luigi.dilillo@lirmm.fr

Program Chairs

Luca Cassano    Politecnico di Milano, Italy    luca.cassano@polimi.it
Sreejit Chakravarty    Intel    sreejit.chakravarty@intel.com

Special Session

Kanad Basu    University of Texas, United States    kanad.basu@utdallas.edu

Publicity

Pedro Reviriego    Universidad Carlos III de Madrid, Spain    revirieg@it.uc3m.es
Majed Valad Beigi    AMD    majed.valadbeigi@amd.com

Industrial Liason

Stephan Eggerglues    Siemens, Germany    stephan_eggersgluess@mentor.com
Sudhanva Gurumurthi    AMD    sudhanva.gurumurthi@amd.com

Publication

Alberto Bosio    École Central de Lyon, France    alberto.bosio@ec-lyon.fr

Audio/Visual

Lucas Matana Luza    LIRMM, France    lucas.matana-luza@lirmm.fr
Andre Mattos    LIRMM, France    andre.martins-pio-de-mattos@lirmm.fr

Web

Douglas Santos    LIRMM, France    douglas.almeida-dos-santos@lirmm.fr

征稿信息

重要日期

2022-05-07
初稿截稿日期
2022-07-08
初稿录用日期

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest. 

征稿范围

  1. Yield Analysis and Modeling
    Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
  2. Testing Techniques
    Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
  3. Design For Testability in IC Design
    FPGA, SoC, NoC, ASIC, low power design and microprocessors.
  4. Error Detection, Correction, and Recovery
    Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
  5. Dependability Analysis and Validation
    Fault injection techniques and frameworks; dependability and characterization.
  6. Repair, Restructuring and Reconfiguration
    Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
  7. Radiation effects
    SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
  8. Defect and Fault Tolerance
    Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
  9. Aging and Lifetime Reliability
    Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
  10. Dependable Applications and Case Studies
    Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
  11. Emerging Technologies
    Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc.
  12. Design for Security
    Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.
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重要日期

  • 会议日期

    10月12日

    2022

    至

    10月14日

    2022

  • 05月07日 2022

    初稿截稿日期

  • 07月08日 2022

    初稿录用通知日期

  • 10月14日 2022

    注册截止日期

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