The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) is the premier event in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern Embedded Systems, Cyber-Physical Systems (CPS), and Internet-of-Things (IoT), from system-level specification and optimization to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.
Sponsor Type:1; 1; 9
Program Chairs
Jason Xue
City University of Hong Kong
Chengmo Yang
University of Delaware
Topics of interest include:
Track 1) System-level design – Specification, modelling, refinement, synthesis, and partitioning of embedded systems, hardware-software co-design, design space exploration, hybrid system modeling and design, model-based design, design for adaptivity and reconfigurability.
Track 2) Domain and application-specific design –Analysis, design, and optimization techniques for multimedia, medical, automotive, cyber-physical, IoT, neural network, and other application domains.
Track 3) Embedded software – Language and library support, compilers, runtimes, parallelization, software verification, memory management, virtual machines, operating systems, real-time support, middleware.
Track 4) System architecture – Heterogeneous systems, many-cores, networked and distributed systems, architecture and micro-architecture design, exploration and optimization including application-specific processors and accelerators, reconfigurable and self-adaptive architectures, storage, memory systems, and networkson-chip.
Track 5) Simulation, validation and verification – Hardware/software co-simulation, verification and validation methodologies, formal verification, hardware accelerated simulation, simulation and verification languages, models, and benchmarks.
Track 6) Safety, security and reliability – Cross-layer reliability, resilience and fault tolerance, test methodology, design for security, reliability, and testability, hardware security, security for embedded, CPS, and IoT devices.
Track 7) Power-aware systems – Power-aware and energy-aware system design and methodologies, ranging from low-power embedded and cyber-physical systems, IoT devices, to energy-efficient large-scale systems such as cloud datacenters, green computing, and smart grids.
Track 8) Embedded machine learning – Hardware and software design, implementation, and optimization for machine learning that are specially designed for resourceand power-constrained embedded, CPS, and IoT devices.
Track 9) Industrial practices and case studies – Practical impact on current and/or future industries, application of state-of-the-art methodologies and tools in various application areas including wireless, networking, multimedia, automotive, cyber-physical, medical systems, IoT, etc
10月10日
2021
10月15日
2021
初稿截稿日期
初稿录用通知日期
注册截止日期
2018年09月30日 意大利
2018 International Conference on Hardware/Software Codesign and System Synthesis2017年10月15日 韩国 Seoul
2017 International Conference on Hardware/Software Codesign and System Synthesis2015年10月04日 荷兰
2015年硬件/软件协同设计和系统合成国际会议2013年09月29日 加拿大
2013年硬件/软件协同设计和系统合成国际会议
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