会议简介

中国计量测试学会 集成电路测试专业委员会

2019年学术年会通知

 

尊敬的专家:您好!

     为了促进我国集成电路测试领域的产学研交流,中国计量测试学会集成电路测试专业委员会决定于2019年8月14日-15日北京九华山庄召开2019年学术年会,就集成电路测试领域的最新研究进展和发展趋势开展广泛、深入的交流。

     我们热诚欢迎从事集成电路测试及相关领域的产学研各界专家、学者和学生参加本次会议。

■ 论坛地点:北京九华山庄(北京市昌平区小汤山镇)

■ 论坛注册费:650元/人

注册参会者可免费参加第十八届全国容错计算学术会议8月15日当天的全部会议日程(http://cftc2019.ccf-ftc.com/

■ 论坛注册费发票:由武汉企泰信息技术有限责任公司开具

■ 论坛程序主席:李华伟(专委秘书长,lihuawei@ict.ac.cn)

■ 论坛联系人:燕洁(18310210016)

■ 注册费说明:

1)注册费含8月14日晚餐、8月15日午餐与晚餐。注册参会者可免费参加第十八届全国容错计算学术会议CFTC2019 8月15日当天的全部会议日程(http://cftc2019.ccf-ftc.com/),并可通过CFTC2019预订酒店房间(http://cftc2019.ccf-ftc.com/hotel.html)。

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· 在线缴费(网银、支付宝、微信、国际信用卡)

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账户名:武汉企泰信息技术有限责任公司
开户行:中国农业银行股份有限公司湖北自贸试验区武汉片区分行
账  号:1706 0101 0400 24567
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· 现场缴费

3)注册费由会务公司“武汉企泰信息技术有限责任公司”开具会议费发票

4)本届会议不退回注册费,请参会人悉知

5)请各位参会者尽可能提前缴费,因特殊情况只能现场缴费的参会者,也请务必提前提交注册信息,以便会务工作人员做现场安排。* 如汇款,请通过上方的注册参会通道进行注册信息填写和汇款,汇款备注里请填写订单编号,银行汇款成功后请务必“上传凭证”,以便财务可及时准确的了解您的缴费情况。

 

■ 温馨提示:

● 上传凭证的方式

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● 发票申请和修改的方式

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会议日程

论坛日程(拟)

8月14日 13:00-14:30 注册报道
14:30-17:30 集成电路测试专委工作会议
8月15日 第一届集成电路测试高峰论坛
14:00-14:10 开幕
14:10-14:50

Keynote 1:题目待定
李晓维,中国科学院计算技术研究所 研究员

Bio: 李晓维,现任中国科学院计算所研究员(中国科学院大学教授)、计算所学位评定委员会副主席,计算机体系结构国家重点实验室常务副主任。获国家技术发明奖、国家科技进步奖;入选国家百千万人才工程和科技北京百名领军人才培养工程,获突出贡献中青年专家、全国优秀科技工作者等荣誉称号。现任中国计算机学会理事、会士、JCST副主编。IEEE CS TTTC 副主席,IEEE TCAD、JETTA等国际期刊编委。

14:50-15:30

Keynote 2:LSI Test: from Research to Business

温暁青,日本九州工业大学 教授,IEEE Fellow

Abstract: LSI test is a core technical field for a successful semiconductor industry due to its indispensability in achieving quality, reliability, safety, security, and cost goals for LSI products. This talk provides a holistic overview of LSI test from both research and business perspectives. Major challenges and opportunities in LSI test are also discussed.

Bio: Xiaoqing WEN received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. He was an Assistant Professor with Akita University, Japan, frrom 1993 to 1997, and a Visiting Researcher with the University of Wisconsin–Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc., USA, in 1998, and served as its Vice President and Chief Technology Officer until 2003. He joined Kyushu Institute of Technology, Japan, in 2003, where he is currently a Professor of the Department of Computer Science and Networks. He founded Dependable Integarted Systems Research Center at Kyushu Institute of Technology in 2013 and served as its Director until 2015. He is a Co-Founder and Co-Chair of Technical Activity Committee on Power-Aware Testing under Test Technology Technical Council (TTTC) of IEEE Computer Society. He is an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Journal of Electronic Testing: Theory and Applications (JETTA). He co-authored and co-edited two popular books, VLSI Test Principles and Architectures: Design for Testability (2006) and Power-Aware Testing and Test Strategies for Low Power Devices (2009). His research interests include design, test, and diagnosis of VLSI circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Infromation Systmes Society (ISS) of Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE, a Councillor of Japan Micro-Nano Bubble Society Corporation (MNBSC), a Senior Member of Information Processing Society of Japan (IPSJ), and a Senior Member IEICE.

15:30-15:50 茶歇
15:50-16:30

Keynote 3:A Detective Story of the Clock Network in an IC — Finding the Timing Failure Threats
黃錫瑜,新竹清华大学 教授

Abstract: For a IC used in safety-critical applications, very high manufacturing quality is often needed in order to ensure almost zero failure rate when it is operated in the field. To achieve this goal, not only the major functional blocks (such as the CPUs and the memory), but also the logistic infrastructure such as the clock network needs to be tested thoroughly. However, a clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this talk, we play the role as a detective to seek out if there is any small delay fault in a clock network. A novel “flush test procedure” will be introduced in particular which drives the clock distribution network with a sequence of pulse signals with decreasing pulse widths, and thereby the delay of each clock path leading to a flip-flop can be quantified and a defect causing too much extra delay can be exposed and identified by outlier analysis. This method is non-intrusive in the sense that it does not need to modify the clock network at all. It does require a “special test clock signal”, which can be generated on the chip by a circuit made of only standard cells. Experimental results show that the proposed method is capable of detecting a less than 100ps delay fault.

Bio: Prof. Shi-Yu Huang received his B.S. and M.S. degrees in Electrical Engineering from Taiwan University in 1988 and 1992, respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of California, Santa Barbara, in 1997. He joined the faculty of the Electrical Engineering Department, Tsing Hua University, Taiwan, in 1999.
He has published more than 150 refereed technical papers, and ever co-founded a company in 2007-2012, TinnoTek Inc., specializing a cell-based PLL compiler and system-level power estimation tools. He received the Best-Presentation or Best-Paper Awards five times from IEEE technical meetings (VLSI-DAT’06, VLSI-DAT’13, ATS’14, WRTLT’17, ISOCC’18, respectively), and his current research interests are mainly the cell-based timing circuit designs and their applications to VLSI Testing and Online Monitoring.

16:30-17:10

Keynote 4:基于深度学习的模拟电路故障诊断与预测关键技术
何怡刚,武汉大学 教授

Abstract: 研究了模拟电路主要元件在退化过程中参数变化的规律,提出了可应用于模拟电路的特征参量优选方法,以及定量地表征模拟电路元件的退化程度。提出了粒子滤波算法和相关向量机算法的优化方法,并基于优化的粒子滤波算法和相关向量机算法,提出了精度高和实时性强的模拟电路故障诊断与预测算法。研究成果对于提高复杂电子系统可靠性、安全性和任务成功性,提高保障效能、降低保障费用具有重要意义。

Bio: 何怡刚  , 国家杰出青年科学基金获得者,教育部新世纪优秀人才,教育部霍英东教育基金会优秀青年教师奖获得者,全国优秀科技工作者。
1996年6月于西安交通大学获博士学位, 2002年在英国University of Hertfordshire从事高访研究。1992至2011年湖南大学电路系统测试技术研究所所长。2011年至2017年,合肥工业大学电气与自动化工程学院院长、博导。目前任武汉大学电气与自动化学院副院长。
长期从事模拟电路与集成电路设计测试与诊断、通讯信道建模与监测、虚拟仪器与智能信号处理等研究工作,先后主持国家科技重大专项、863、973、国家自然科学基金重点等重要科研项目30多项。
作为第一完成人获得教育部自然科学奖一等奖1项,省部级科技进步一等奖2项、发明一等奖1项。
目前兼任中国能源学会副会长、中国能源科技产业学会副会长、中国电机工程学会电工理论与新技术专委会副主任、中国高校电工学研究会副理事长、中国机械工业教育协会电力系统与自动化专业教学指导委员会副主任、中国计算机自动测量与控制技术协会常务理事、中国计算机学会容错专委会常委、中国仪器仪表行业协会传感器分会理事、可再生能源接入电网技术国家地方联合工程实验室主任、电子测试国防科技重点实验室学术委员会委员、中航工业强电磁环境防护技术航空科技重点实验室学术委员会副主任、电工装备可靠性与智能化国家重点实验室学术委员会委员。21次担任IEEE国际学术会议大会主席、分会主席和程序委员,国家科技重大专项、国家科技奖励、国家自然基金委评审专家。

 

17:10-18:00 Panel:集成电路测试教育教学与培训

 

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