144 / 2019-06-13 21:10:22

2.5 GHz Data Rate 2xVDD Digital Output Buffer Design Realized by 16-nm FinFET CMOS

FinFET,output buffer,PVT,slew rate,mixed

A 2VDD output buffer featured with PVT (process, voltage, temperature) corner detection and SR (slew rate) self-adjustment is proposed in this investigation. Notably, the proposed buffer design is realized by 16-nm FinFET CMOS technology. To enhance the output SR (slew rate), always on
driving transistors in Output Stage must be realized with low Vth devices to boost the output current. Nonoverlapping signal generator is directly realized in transistor level instead of conventional gate level designs such that the the speed is fastened. According to the all-PVT-corner simulations, the
worst data rate is 2.5/2.5 GHz given 0.8/1.6 V supply voltage with 20 pF load, respectively. The Δ SR improvement is at least 10%, when the proposed SR self-adjustment mechanism is activated.