活动简介

The fourth joint EUROSOI-ULIS event will be hosted by the University of Granada in Granada, Spain. The focus of the sessions is on advanced nanoscale devices, including SOI technology. Papers in the following areas are solicited: Physical mechanisms and innovative SOI-like devices. New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials. Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications. New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.

征稿信息

重要日期

2018-01-12
摘要截稿日期
2018-01-30
摘要录用日期
2018-02-23
终稿截稿日期

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The accepted abstracts will be published in a Proceedings book with an ISBN. A 4-page follow-up paper, delivered before February 23, 2018 will be reviewed and published at the IEEE Xplore Digital Library. The authors of the best papers will be invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Papers in the following areas are solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.
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重要日期
  • 会议日期

    03月19日

    2018

    03月21日

    2018

  • 01月12日 2018

    摘要截稿日期

  • 01月30日 2018

    摘要录用通知日期

  • 02月23日 2018

    终稿截稿日期

  • 03月21日 2018

    注册截止日期

主办单位
IEEE
承办单位
Facultad de Ciencias
Universidad de Granada
Research Center for Information & Communication Technologies
Universidad de Granada
Universidad de Granada
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