The Design and Verification Conference & Exhibition India (DVCon India) is a highly technical conference in India targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India 2017 is patterned on the successful DVCon United States conference held for over 10 years in the Silicon Valley.
The ultimate goal of DVCon India 2017 is to boost the interest, usage and development of electronic system designs. We look forward to users sharing the various challenges and solutions adopted by various teams across the industry. DVCon India also provides a much-needed platform to promote upcoming Electronic Design Automation (EDA) and Intellectual Property (IP) standards in India. This 2-day conference is organized to invite industry practitioners to learn and share best practices on:
Modeling, Design and Verification of complex electronic systems at different levels of abstraction such as Virtual prototyping, Architectural Modeling, RTL, Emulation, HW acceleration, etc.
The application of system-level design and verification languages such as SystemC, SystemVerilog, PSL, e, VHDL etc for digital designs and Verilog-AMS for Analog Mixed Signal designs
Virtual Platform for Embedded Software Development
SoC Design Verification using the latest trends and methodologies such as UVM-SystemC, graph-based techniques, portable stimulus across block-subsystem-system all the way up to Post-Silicon
Architectural Exploration at the early stage and High-level Synthesis
The use of SystemVerilog Assertions (SVA), Property Specification Language Assertions (PSL) and Formal Verification Techniques (Model Checking)
Adoption of Universal Verification Methodology (UVM)
Leveraging on legacy methodologies based on OVM, VMM and migration to UVM
IP reuse, design automation and integration standards based on IP-XACT and SystemRDL
Low-power design and verification using the Unified Power Format (UPF)
General topic areas on Electronic System Level (ESL), Virtual Platform, Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low-power design and verification will be highlighted in tutorials, papers, and poster sessions.
Conference attendees are primarily designers of embedded systems, electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration solutions. The DVCon India 2016 conference attracts a highly skilled user base active in various industries focusing on research and development of automotive, aerospace, consumer, medical, and wired and wireless communication products.
Using multiple HDLs and/or HVLs in a design cycle
Novel application of existing standard DV (Design-Verification) languages such as SystemVerilog, PSL, e, VHDL, etc.
Latest language developments in SystemVerilog
Advanced stimulus generation methods, reuse of stimulus across levels of pre/post silicon testing (portable stimulus)
System-on-Chip (SoC) Verification approaches to handle complexity, performance and reusability requirements including HW/SW cosin environments
UVM adoption, advanced techniques/features and extensions
Real life applications of assertions using SVA and/or PSL
Formal and semi-formal techniques, Assertion automation/synthesis
Verification process and resource management
Compliance and requirements-driven verification such as DO-254 standards
Debug automation through transaction-level debug, smart tricks to handle simulation performance issues, faster time to debug techniques
Low Power intent verification through standards such as UPF and related technologies
Usage of IPXACT and SystemRDL in design flow
AMS challenges in Verification, usage of custom extensions to UVM/SystemVerilog to handle AMS related complexities
RF/Very high-speed designs (including SerDes) related verification challenges and tricks used in practice
Testbench Acceleration techniques to meet modern ultra-complex chip verification challenges - case studies and experiences
Functional Coverage closure techniques and its testbench design implications
09月14日
2017
09月15日
2017
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