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活动简介

Aims and Objectives

The purpose of ATVA is to promote research on theoretical and practical aspects of automated analysis, verification and synthesis by providing a forum for interaction between the regional and the international research communities and industry in the field.

Highlights

  • Three days of high-quality research presentations
  • Three keynote lectures (hardware verification, software verification and theory)
  • One day of tutorials by the three keynote speakers
征稿信息

重要日期

2017-04-28
初稿截稿日期
2017-06-15
初稿录用日期
2017-07-10
终稿截稿日期

征稿范围

ATVA 2017 is the 15th in a series of symposia aimed at bringing together academics, industrial researchers and practitioners in the area of theoretical and practical aspects of automated analysis, synthesis, and verification of hardware and software systems. ATVA solicits high quality submissions in the following suggestive list of topics:

  • Formalisms for modeling hardware, software and embedded systems
  • Specification and verification of finite-state, infinite-state and parameterized system
  • Program analysis and software verification
  • Analysis and verification of hardware circuits, systems-on-chip and embedded systems
  • Analysis of real-time, hybrid, priced, weighted and probabilistic systems
  • Deductive, algorithmic, compositional, and abstraction/refinement techniques for analysis and verification
  • Analytical techniques for safety, security, and dependability
  • Testing and runtime analysis based on verification technology
  • Analysis and verification of parallel and concurrent systems
  • Verification in industrial practice
  • Synthesis for hardware and software systems
  • Applications and case studies
  • Automated tool support
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重要日期
  • 会议日期

    10月03日

    2017

    10月06日

    2017

  • 04月28日 2017

    初稿截稿日期

  • 06月15日 2017

    初稿录用通知日期

  • 07月10日 2017

    终稿截稿日期

  • 10月06日 2017

    注册截止日期

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