Machine Learning Classification Algorithm for VLSI Test Cost Reduction
编号:91
访问权限:仅限参会人
更新:2021-12-07 10:19:44 浏览:206次
口头报告
摘要
With the growing complexity of integrated circuits (ICs), more and more test patterns (TP) are required so as to detect more defects. However, a large number of invalid patterns (pattern that can make the test pass) continues to increase test time (TT) and, consequently, Test Cost (TC) . Considering the problem that TT is too long and TC is increasing, this paper proposes an improved K-Nearest Neighbor (KNN) algorithm to select the valid patterns (pattern that can make the test fail) only. Experimental results demonstrate that the proposed method succeed in reducing 1.75 times TT compared with the traditional method with all patterns. In addition, the improved KNN algorithm aims at using the minimum number of TP to discover the maximum number of defects, which can reduce TT without increasing the number of defects obviously. Furthermore, the experimental results represent the optimal compromise between TC
and test quality (TQ).
关键词
VLSI test;machine learning (ML);test patterns (TP);test cost (TC)
稿件作者
SongTai
Anhui University;Hefei University of Technology; Anhui Polytechnic University
发表评论