Scaling of aerospace integrated circuits to nanoscale feature sizes, has decreased the effectiveness of existing single-node-upset and double-node-upset hardened techniques in the harsh radiation environment. This paper proposes a low-power triple-node-upset-resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. The proposed LP-TNU achieves the TNU resilience based on the filtering feature of the C-element and redundant feedback structure. Extensive simulation results demonstrate the robustness of the proposed latch. The proposed LP-TNU achieves the extremely low power consumption because of clock-gating technique and fewer transistors. Compared with reference latches, the proposed latch is the most robust with the lowest power consumption and power-delay-product. In addition, compared with equivalent TNU-resilient latches such as DNUHL, LCTNURL, and TNURL, the proposed LP-TNU achieves 62.53% reduction on average in power consumption, 31.04% reduction on average in delay, 19.75% reduction on average in area overhead, 76.83% reduction on average in the area-power-delay product. At the same time, the proposed latch is insensitive to variations in supply voltage and working temperature.

Hardened latch design; Low power; Approximate c-elements; Triple-node-upset-resilience