The calculation of coarse-grained reconfigurable execution unit has become a research hotspot at home and abroad. The design and simulation of its calculation module are the key of coarse-grained reconfigurable execution unit, and it is also one of the key steps of the practicality and generalization of reconfigurable computing. In this paper, the circuit simulation and design of the traditional classical signed true form addition, subtraction, multiplication and division are carried out; The operation bits are 4,8,16,32,64 respectively. Verilog HDL is used to analyze and compare the dynamic power consumption, junction temperature, LUT and I/O number of adders, subtracters, multipliers and dividers in the case of 4bit, 8bit, 16bit, 32bit and 64bit, and the simulation schematic diagram and test code of four operations are designed respectively. The experimental results show that compared with 4bit operation, the dynamic power consumption of 8-bits, 16 bits, 32-bits and 64 bits operation increase by 4.12w, 11.1w, 24.8w and 52.4w respectively; The number of LUTS increased by 37, 85, 181 and 373, respectively; The number of I/O increased by 12, 36, 84 and 180 respectively; The junction temperature increased by 0.83℃, 2.22℃, 4.97℃ and 10.48℃ respectively. Compared with multiplier and divider, the dynamic power consumption, junction temperature, LUT and I/O consumption of adder and subtractor are lower. For the junction tem-perature failure, this paper also gives a specific solution. In addition, a clock driver is added to display and calculate the cycle consumed by each calculator.

Coarse-grained reconfigurable; True form; Junction temperature; LUT; I/O; Dynamic power