Advanced Encryption Standard(AES) is one of the most popular cryptographic algorithms today, hardware AES architecture is widely used and usually implemented in CMOS technology. However, the downscaling of CMOS technology leads the hardware implemented AES to suffer from low reliability due to permanent faults (PFs) and transient faults (TFs). This paper investigates a reliable architecture for compact ASIC implemented Advanced Encryption Standard processors. We propose a reliability enhanced technique based on the inherent and temporal redundancy. By merging this technique with hardware redundancy schemes, the hybrid architecture can cope with both transient and permanent faults with a low area overhead. Results obtained with 65nm show a good trade-off of the hybrid solution between reliability improvement and area cost.

Fault Tolerance; Advanced Encryption Standard (AES); Triple Modular Redundancy(TMR); Dynamic Hardware Redundancy(DHR)