We will give an overview of some recent results on 3D integration of CMOS and memristive memory arrays and demonstrate its potential of offering very high memory density and bandwidth at manageable power dissipation, and enabling new memory-centric computing paradigms for AI applications.
It has been recognized that such resistive memory cells still suffer from multiple limitations including high energy consumption for programming, limited endurance, and large cycle-to-cycle and device-to-device variations. We will highlight research directions and some recent solutions addressing these limitations.
Finally, we will discuss recent development and research opportunities of an application-specific co-design framework which closely integrates application-specific neural network search, hardware-friendly network compression and NN-aware architecture design for iterative co-optimization.
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