Selective Harmonic Elimination Control for Cascaded Digital Power Amplifier
编号:253 访问权限:仅限参会人 更新:2020-10-15 21:00:47 浏览:273次 口头报告

报告开始:2020年11月04日 09:45(Asia/Shanghai)

报告时间:15min

所在会场:[B] Power Electronics Technology and Application [B3] Session 23 and Session 28

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摘要
In this paper, the selective harmonic elimination (SHE) strategy for cascaded digital power amplifier is derived and proposed. To solve the problem of slow iteration speed or even non-convergence of the traditional iterative method when the number of levels or the number of harmonic elimination equations is large, a new solution method based on "interior point method” is introduced. In practical application the dead-time cannot be avoided, so the impact of dead-time on selective harmonic elimination strategy is also analyzed. Based on the relationship between output voltage and current during dead-time, the control method of “flexible insertion of dead-time on line” is proposed, which can significantly weaken the dead-time effect on selective harmonic elimination strategy in practice.
关键词
selective harmonic elimination, interior point method, dead-time effect elimination
报告人
Junyao Tu
Huazhong University of Science and Technology

稿件作者
Junyao Tu Huazhong University of Science and Technology
Hengyang Liu Huazhong University of Science and Technology
Wubin Kong Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology
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重要日期
  • 会议日期

    11月02日

    2020

    11月04日

    2020

  • 10月27日 2020

    初稿截稿日期

  • 11月03日 2020

    报告提交截止日期

  • 11月04日 2020

    注册截止日期

  • 11月17日 2020

    终稿截稿日期

主办单位
IEEE IAS Student Chapter of Huazhong University of Science and Technology (HUST)
承办单位
Huazhong University of Science and Technology
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