摘要详情
121 / 2021-04-09 13:35:50
8G Physical Coding Sub-layer design based on PCI Express 3.0 protocol under 40nm process
PCI Express 3.0, PCS, Data width adjustment, Data Alignment, Elastic Buffer
终稿
Abstract—The PCI Express bus is a widely used high-speed serial bus standard. The PCS layer, as a sub-layer of the physical layer of the PCIe three-layer architecture, has an important status. A PCS layer circuit is designed based on the PCIe 3.0 protocol, which mainly includes data width adjustment circuit, data alignment circuit, elastic buffer and codec circuit. SMIC 40nm CMOS process is used to synthesize the circuit. Under the conditions of 500MHz clock, ss process angle and 125℃ temperature, the area is 69165um², and dynamic power consumption is 9.81mW. Tape tests show that the PCS layer circuit can be combined with the 8Gbps PMA layer to form a discrete physical layer chip, which supports 8GT/s transmission.
重要日期
-
会议日期
07月10日
2021
至07月12日
2021
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05月10日 2021
初稿截稿日期
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07月06日 2021
注册截止日期
主办单位
长沙理工大学
协办单位
IEEE Electron Devices Society
IEEE
IEEE
联系方式
- Dr. WanghuiZou
- zo******@csust.edu.cn
- 135********
历届会议
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2018年05月07日 台湾-中国
2018 7th International Symposium on Next Generation Electronics -
2017年05月23日 台湾-中国 Keelung
2017 6th International Symposium on Next Generation Electronics
