448 / 2019-02-27 15:27:56

Output-Capacitor-Less LDO with High PSR

low-dropout regulator, capacitor-free, Power supply rejection, Q-reduction

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A low-dropout regulator (LDO) with high power supply ripple rejection (PSR) and capacitor-free is presented in this paper. The LDO proposes a PSR enhancement module based on the analysis of the power supply noise transmission path. It uses the Q-reduction circuit to reduce the required on-chip capacitor and the load on the minimum required output. The proposed LDO is implemented in 110nm CMOS process. The simulation results indicate that the total on-chip capacitance required for the designed circuit is 6.5p. The LDO has a phase margin of more than 60° in the range of 50uA to 50mA. The optimum PSR of the LDO at low frequency is -109dB. The LDO achieves line and load regulation of 65μV/V and 0.396μV/mA respectively.